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參數(shù)資料
| 型號： | ADSP-2104LKP-55 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Low Cost DSP Microcomputers |
| 中文描述： | 24-BIT, 13.824 MHz, OTHER DSP, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 3/36頁 |
| 文件大?。?/td> | 333K |
| 代理商： | ADSP-2104LKP-55 |
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ADSP-2104/ADSP-2109
REV. 0
–3–
ARCHIT E CT URE OVE RVIE W
Figure 1 shows a block diagram of the ADSP-2104/ADSP-2109
architecture. T he processor contains three independent compu-
tational units: the ALU, the multiplier/accumulator (MAC), and
the shifter. T he computational units process 16-bit data directly
and have provisions to support multiprecision computations.
T he ALU performs a standard set of arithmetic and logic
operations; division primitives are also supported. T he MAC
performs single-cycle multiply, multiply/add, and multiply/
subtract operations. T he shifter performs logical and arithmetic
shifts, normalization, denormalization, and derive exponent
operations. T he shifter can be used to efficiently implement
numeric format control including multiword floating-point
representations.
T he internal result (R) bus directly connects the computational
units so that the output of any unit may be used as the input of
any unit on the next cycle.
A powerful program sequencer and two dedicated data address
generators ensure efficient use of these computational units.
T he sequencer supports conditional jumps, subroutine calls,
and returns in a single cycle. With internal loop counters and
loop stacks, the ADSP-2104/ADSP-2109 executes looped code
with zero overhead—no explicit jump instructions are required
to maintain the loop. Nested loops are also supported.
T wo data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four
address pointers. Whenever the pointer is used to access data
(indirect addressing), it is post-modified by the value of one of
four modify registers. A length value may be associated with
each pointer to implement automatic modulo addressing for
circular buffers. T he circular buffering feature is also used by
the serial ports for automatic data transfers to (and from) on-
chip memory.
Efficient data transfer is achieved with the use of five internal
buses:
Program Memory Address (PMA) Bus
Program Memory Data (PMD) Bus
Data Memory Address (DMA) Bus
Data Memory Data (DMD) Bus
Result (R) Bus
T he two address buses (PMA, DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD, DMD) share a single external data bus.
T he
BMS
,
DMS
, and
PMS
signals indicate which memory
space is using the external buses.
Program memory can store both instructions and data, permit-
ting the ADSP-2104/ADSP-2109 to fetch two operands in a
single cycle, one from program memory and one from data
memory. T he processor can fetch an operand from on-chip
program memory and the next instruction in the same cycle.
T he memory interface supports slow memories and memory-
mapped peripherals with programmable wait state generation.
External devices can gain control of the processor’s buses with
the use of the bus request/grant signals (
BR
,
BG
).
One bus grant execution mode (GO Mode) allows the ADSP-
2104/ADSP-2109 to continue running from internal memory.
A second execution mode requires the processor to halt while
buses are granted.
Figure 1. ADSP-2104/ADSP-2109 Block Diagram
R Bus
16
DMD BUS
PMD BUS
DMA BUS
PMA BUS
14
24
16
EXTERNAL
ADDRESS
BUS
EXTERNAL
DATA
BUS
BOOT
ADDRESS
GENERATOR
TIMER
14
BUS
EXCHANGE
COMPANDING
CIRCUITRY
5
16
24
DMA BUS
PMA BUS
DMD BUS
PMD BUS
PROGRAM
SEQUENCER
INSTRUCTION
REGISTER
PROGRAM
MEMORY
SRAM
or ROM
DATA
MEMORY
SRAM
DATA
ADDRESS
GENERATOR
#2
DATA
ADDRESS
GENERATOR
#1
14
INPUT REGS
OUTPUT REGS
SHIFTER
INPUT REGS
OUTPUT REGS
MAC
INPUT REGS
OUTPUT REGS
ALU
RECEIVE REG
SERIAL
PORT 0
TRANSMIT REG
MUX
24
MUX
5
RECEIVE REG
SERIAL
PORT 1
TRANSMIT REG
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