參數(shù)資料
型號(hào): ADSP-2104KP-80
廠商: ANALOG DEVICES INC
元件分類: 數(shù)字信號(hào)處理
英文描述: Low Cost DSP Microcomputers
中文描述: 24-BIT, 20 MHz, OTHER DSP, PQCC68
封裝: PLASTIC, LCC-68
文件頁數(shù): 30/36頁
文件大?。?/td> 333K
代理商: ADSP-2104KP-80
ADSP-2104/ADSP-2109
–30–
REV. 0
TIMNGPARAMETERS (ADSP-2104L/ADSP-2109L)
BUS RE QUE ST /GRANT
Frequency
Dependency
Min
13.824 MHz
Min
Parameter
Max
Max
Unit
Timing Requirement:
t
BH
BR Hold after CLKOUT High
1
t
BS
BR Setup before CLKOUT Low
1
Switching Characteristic:
t
SD
CLKOUT High to DMS, PMS, BMS, RD, WR Disable
t
SDB
DMS, PMS, BMS, RD, WR Disable to BG Low
t
SE
BG High to DMS, PMS, BMS, RD, WR Enable
t
SEC
DMS, PMS, BMS, RD, WR Enable to CLKOUT High
23.1
38.1
0.25t
CK
+ 5
0.25t
CK
+ 20
ns
ns
38.1
0.25t
CK
+ 20
ns
ns
ns
ns
0
0
8.1
0
0
0.25t
CK
– 10
NOTES
1
If BR meets the t
and t
setup/hold requirements, it will be recognized in the current processor cycle; otherwise it is recognized in the following cycle. BR
requires a pulse width greater than 10 ns.
Note: BG is asserted in the cycle after BR is recognized. No external synchronization circuit is needed when BR is generated as an asynchronous signal.
Figure 27. Bus Request/Grant
CLKOUT
PMS
,
DMS
BMS
,
RD
WR
BR
BG
CLKOUT
t
SD
t
SDB
t
SE
t
SEC
t
BH
t
BS
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