參數(shù)資料
型號(hào): ADSP-2104KP-80
廠商: ANALOG DEVICES INC
元件分類(lèi): 數(shù)字信號(hào)處理
英文描述: Low Cost DSP Microcomputers
中文描述: 24-BIT, 20 MHz, OTHER DSP, PQCC68
封裝: PLASTIC, LCC-68
文件頁(yè)數(shù): 29/36頁(yè)
文件大?。?/td> 333K
代理商: ADSP-2104KP-80
ADSP-2104/ADSP-2109
REV. 0
–29–
TIMNGPARAMETERS (ADSP-2104L/ADSP-2109L)
INT E RRUPT S & FLAGS
Frequency
Dependency
13.824 MHz
Min
Parameter
Max
Min
Max
Unit
Timing Requirement:
t
IFS
IRQx
1
or FI Setup before CLKOUT Low
2, 3
t
IFH
IRQx
1
or FI Hold after CLKOUT High
2, 3
Switching Characteristic:
t
FOH
FO Hold after CLKOUT High
t
FOD
FO Delay from CLKOUT High
33.1
18.1
0.25t
CK
+ 15
0.25t
CK
ns
ns
0
ns
ns
15
NOTES
1
IRQx=IRQ0, IRQ1, and IRQ2
.
2
If IRQx and FI inputs meet t
IFS
and t
IFH
setup/hold requirements, they will be recognized during the current clock cycle; otherwise they will be recognized during the
following cycle. (Refer to the “Interrupt Controller” section in Chapter 3, Program Control, of the
ADSP-2100 Family User’s Manual
for further information on
interrupt servicing.)
3
Edge-sensitive interrupts require pulse widths greater than 10 ns. Level-sensitive interrupts must be held low until serviced.
Figure 26. Interrupts & Flags
CLKOUT
FLAG
OUTPUT(S)
t
FOD
IRQ
x
FI
t
FOH
t
IFH
t
IFS
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