參數(shù)資料
型號(hào)： ADSP-2100A
廠商： Analog Devices, Inc.
英文描述： ADSP-2100 Family DSP Microcomputers
中文描述： 的ADSP - 2100系列DSP的微機(jī)
文件頁(yè)數(shù)： 47/64頁(yè)
文件大小： 668K
代理商： ADSP-2100A
ADSP-21xx
REV. B
–47–
TIMNGPARAMETERS (ADSP-2103/2162/2164)
BUS RE QUE ST /GRANT
Frequency
Dependency
Min
10.24 MHz
Min
Parameter
Max
Max
Unit
Timing Requirement:
t
BH
BR Hold after CLKOUT High
1
t
BS
BR Setup before CLKOUT Low
1
Switching Characteristic:
t
SD
CLKOUT High to DMS, PMS, BMS, RD, WR Disable
t
SDB
DMS, PMS, BMS, RD, WR Disable to BG Low
t
SE
BG High to DMS, PMS, BMS, RD, WR Enable
t
SEC
DMS, PMS, BMS, RD, WR Enable to CLKOUT High
29.4
44.4
0.25t
CK
+ 5
0.25t
CK
+ 20
ns
ns
44.4
0.25t
CK
+ 20
ns
ns
ns
ns
0
0
14.4
0.25t
CK
– 10
NOTES
1
If BR meets the t
and t
setup/hold requirements, it will be recognized in the current processor cycle; otherwise it is recognized in the following cycle. BR
requires a pulse width greater than 10 ns.
Section 10.2.4, “Bus Request/Grant,” of the
ADSP-2100 Family User’s Manual (1st Edition, 1993)
states that “When BR is recognized, the processor
responds immediately by asserting BG during the same cycle.” This is incorrect for the current versions of all ADSP-21xx processors: BG is asserted in the
cycle after BR is recognized. No external synchronization circuit is needed when BR is generated as an asynchronous signal.
Figure 41. Bus Request/Grant
CLKOUT
PMS
,
DMS
BMS
,
RD
WR
t
BS
BR
BG
CLKOUT
t
SD
t
SDB
t
SE
t
SEC
t
BH
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