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參數(shù)資料
| 型號： | ADS8517IDW |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PDSO28 |
| 封裝： | GREEN, PLASTIC, SOIC-28 |
| 文件頁數(shù)： | 35/38頁 |
| 文件大?。?/td> | 948K |
| 代理商： | ADS8517IDW |
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SLAS527A – SEPTEMBER 2008 – REVISED JUNE 2009 ................................................................................................................................................. www.ti.com
PIN ASSIGNMENTS (continued)
Data clock. Either an input or an output, depending on the EXT/INT level. Output data are
DATACLK
18
I/O
synchronized to this clock. If EXT/INT is low, DATACLK transmits 16 pulses after each
conversion, and then remains low between conversions.
Serial data output. Data are synchronized to DATACLK, with the format determined by the level
of SB/BTC. In the external clock mode, after 16 bits of data, the ADC outputs the level input on
SDATA
19
O
TAG as long as CS is low and R/C is high. If EXT/INT is low, data are valid on both the rising
and falling edges of DATACLK, and between conversions SDATA stays at the level of the TAG
input when the conversion was started.
Tag input for use in the external clock mode. If EXT is high, digital data input from TAG is output
TAG
20
I
on DATA with a delay that depends on the external clock mode.
Byte select. Selects the eight most significant bits (low) or eight least significant bits (high) on
BYTE
21
I
parallel output pins.
Read/convert input. With CS low, a falling edge on R/C puts the internal sample-and-hold circuit
R/C
22
I
into the hold state and starts a conversion. With EXT/INT is low, the transmission of the data
results from the previous conversion is initiated.
Chip select. Internally ORed with R/C. If R/C is low, a falling edge on CS initiates a new
CS
23
I
conversion. If EXT/INT is low, this same falling edge will start the transmission of serial data
results from the previous conversion.
Busy output. At the start of a conversion, BUSY goes low and stays low until the conversion is
BUSY
24
O
completed and the digital outputs have been updated.
Power-down input. If high, conversions are inhibited and power consumption is significantly
PWRD
25
I
reduced. Results from the previous conversion are maintained in the output shift register.
Reference disable. REFD high shuts down the internal reference. The external reference is
REFD
26
I
required for conversions.
VANA
27
ADC core supply. Nominally +5 V. Decouple with 0.1-
F ceramic and 10-F tantalum capacitors.
VDIG
28
I/O supply. Nominally +1.8 V.
6
Copyright 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): ADS8517
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| ADS8517IDWG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16B,5V,125KSPS,ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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| ADS8517IDWRG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16B,5V,125KSPS,ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS8517IPW | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Lo Pwr 16B 200kSPS +/-10V Bip InSAR ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS8517IPWR | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Lo Pwr 16B 200kSPS +/-10V Bip InSAR ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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