參數(shù)資料
型號(hào)： ADS8412IPFBTG4
廠(chǎng)商： TEXAS INSTRUMENTS INC
元件分類(lèi)： ADC
英文描述： 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PQFP48
封裝： GREEN, PLASTIC, TQFP-48
文件頁(yè)數(shù)： 14/29頁(yè)
文件大?。?/td> 1018K
代理商： ADS8412IPFBTG4
www.ti.com
_
+
_
+
IN-
IN+
ADS8412
_
+
VCC+
VCC-
1 k
1 k
THS4503
68 pF
50
50
20 pF
RG
RS
RT
OCM
1 k
RG, RS, and RT should be chosen such that
RG + RS || RT = 1 k
VOCM = 2 V, +VCC = 7 V, and -VCC = -7 V
DIGITAL INTERFACE
Timing And Control
Reading Data
ADS8412
SLAS384A – JUNE 2003 – REVISED DECEMBER 2004
PRINCIPLES OF OPERATION (continued)
Figure 31. Using THS4503 With ADS8412
See the timing diagrams in the specifications section for detailed information on timing signals and their
requirements.
The ADS8412 uses an internal oscillator generated clock which controls the conversion rate and in turn the
throughput of the converter. No external clock input is required.
Conversions are initiated by bringing the CONVST pin low for a minimum of 20 ns (after the 20 ns minimum
requirement has been met, the CONVST pin can be brought high), while CS is low. The ADS8412 switches from
the sample to the hold mode on the falling edge of the CONVST command. A clean and low jitter falling edge of
this signal is important to the performance of the converter. The BUSY output is brought high after CONVST
goes low. BUSY stays high throughout the conversion process and returns low when the conversion has ended.
Sampling starts when CS is tied low or starts with the falling edge of CS when BUSY is low.
Both RD and CS can be high during and before a conversion with one exception (CS must be low when
CONVST goes low to initiate a conversion). Both the RD and CS pins are brought low in order to enable the
parallel output bus with the conversion.
The ADS8412 outputs full parallel data in two's complement format as shown in Table 1. The parallel output is
active when CS and RD are both low. There is a minimal quiet zone requirement around the falling edge of
CONVST. This is 50 ns prior to the falling edge of CONVST and 40 ns after the falling edge. No data read should
be attempted within this zone. Any other combination of CS and RD sets the parallel output to 3-state. BYTE is
used for multiword read operations. BYTE is used whenever lower bits of the conversion result are output on the
higher byte of the bus. Refer to Table 1 for ideal output codes.
21
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADS8413 制造商:BB 制造商全稱(chēng):BB 功能描述:16-BIT, 1-MSPS, PSEUDO-BIPOLAR, FULLY DIFFERENTIAL INPUT, MICROPOWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE, REFERENCE
ADS8413IBRGZR 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16-bit Uni Diff In Smp rt 4.75-5.25V RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS8413IBRGZRG4 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16-bit Uni Diff In Smp rt 4.75-5.25V RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS8413IBRGZT 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16-bit Uni Diff In Smp rt 4.75-5.25V RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS8413IBRGZTG4 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16-bit Uni Diff In Smp rt 4.75-5.25V RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
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