參數(shù)資料
型號: ADS7945SRTET
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 2-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PQCC16
封裝: GREEN, PLASTIC, QFN-16
文件頁數(shù): 29/49頁
文件大小: 1322K
代理商: ADS7945SRTET
SBAS539B
– JUNE 2011 – REVISED SEPTEMBER 2011
Table 4 lists the recommended bypass capacitor values and the filter time constant for different source
resistances. It is recommended to use a 10 pF bypass capacitor, at minimum. Table 4 assumes RS = 5 Ω;
however, depending on the application, RS can be chosen to be 0 Ω. In this case, there is an extra margin of 5 Ω
for RSOURCE.
Table 4. Filter Time Constant versus Source Resistance
APPROXIMATE CBYPASS
FILTER TIME
2
× RSOURCE (Ω)
2
× (RSOURCE + RS)
(pF)
CBYPASS + CSAMPLE (pF)
CONSTANT (ns)
18
28
220
252
7.2
44
54
100
132
7.2
81
91
47
79
7.2
161
171
10
42
7.2
500
510
10
42
21
1000
1010
10
42
5000
5010
10
42
210
Typically, settling resolution is selected as (ADC resolution + 2). For the ADS7945 (14-bit) the ideal settling
resolution is 16. Using Equation 2 and Equation 3, the sampling time can be easily determined for a given source
impedance and allows 80 ns of sampling time for a 14-bit ADC with 7.2 ns of filter time constant, which matches
the ADS7945 specifications. For net source impedance (2
× (RSOURCE + RS)) above 171 Ω, the filter time
constant continues to increase beyond the 7.2 ns required for an 80 ns sampling time. This increment increases
the minimum permissible sampling time for 14-bit settling and the device must be operated at a lower sampling
rate.
The device sampling rate can be maximized by using a 40 MHz clock even for lower throughputs. Table 5 shows
typical calculations for the ADS7945.
Table 5. Sampling Frequency versus Source Impedance for the ADS7945 (14-Bit)
SAMPLING TIME,
CONVERSION TIME, CYCLE TIME, tACQ +
SAMPLING RATE
2
× RSOURCE (Ω)
CBYPASS (pF)
tACQ (ns)
tCONV (ns)
(MSPS)
420
161
10
80
500
2
(with 40 MHz clock)
420
500
10
235
655
1.5
(with 40 MHz clock)
420
1000
10
468
888
1.1
(with 40 MHz clock)
420
5000
10
2331
2751
0.4
(with 40 MHz clock)
It is necessary to allow 1000 ns additional sampling time over what is shown in Table 5 if PDEN (pin 12) is set
high.
Copyright
2011, Texas Instruments Incorporated
35
Product Folder Link(s): ADS7945 ADS7946
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