參數(shù)資料
型號: ADS7945SRTET
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 2-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PQCC16
封裝: GREEN, PLASTIC, QFN-16
文件頁數(shù): 24/49頁
文件大?。?/td> 1322K
代理商: ADS7945SRTET
1
2
14
15
16
17
27
28
29
30
31
32
SCLK
CS
SDO
t
ACQ
t
CONV
D13
18
Power-DownState
(Internal)
I
DYNAMIC
IPD
DYNAMIC
IPD
.
STATIC
DYNAMIC
if
SCLKisoff,
otherwise
IPD
I
Profile
AVDD
t
ACQ(MIN)+
1 s
m
I
STATIC
D12
D3
D2
D1
D0
SBAS539B
– JUNE 2011 – REVISED SEPTEMBER 2011
CS can be held low past the 16th falling edge of SCLK. The devices continue to output recently converted data
starting with the 16th SCLK falling edge. If CS is held low until the 30th SCLK falling edge, then the devices
detect 32-clock mode. Note that the device data from recent conversions are already output with no latency
before the 30th SCLK falling edge. Once 32-clock mode is detected, the device outputs 16 zeros during the next
conversion (in fact, for the first 16 clocks), unlike 16-clock mode where the devices output the previous
conversion result. SCLK can be stopped after the devices have seen the 30th falling edge with CS low.
CONVERSION ABORT
For some event triggered applications such as latching position of absolute position sensor on marker or homing
pulse, it is essential to abort ongoing conversion on event and quickly start fresh acquisition. ADS794X features
conversion abort function. CS high during conversion (during first 16 clocks) will abort ongoing conversion and
start fresh acquisition. Device will sample acquired signal during CS high period on falling edge of CS and will
start conversion normally, however data on SDO (conversion results from aborted frame) will not be valid.
For example if conversion is aborted during
‘nth’ frame and (n+1) is first valid frame after conversion abort. SDO
data during frame number (n+1) (corresponding to nth conversion) will not be valid. Conversion results for sample
and conversion during frame number (n+1) will be available in frame number (n+2).
POWER-DOWN
The ADS7945/6 devices offer an easy-to-use power-down feature available through a dedicated PDEN pin (pin
12). A high level on PDEN at the CS rising edge enables the power-down mode for that particular cycle.
Figure 83 to Figure 85 illustrate device operation with power-down in both 32-clock and 16-clock mode.
Many applications must slow device operation. For speeds below approximately 500 kSPS, it is convenient to
use 32-clock mode with power-down. This configuration results in considerable power savings.
As shown in Figure 83, PDEN is held at a logic '1' level. Note that the device looks at the PDEN status only at
the CS rising edge; however, for continuous low-speed operation, it is convenient to continuously hold PDEN = 1.
The devices detect power-down mode on the CS rising edge with PDEN = 1.
Figure 83. Operation with a 32-Clock Frame in Power-Down Mode (PDEN = 1)
On the CS falling edge, the devices start normal operation as previously described. The devices complete
conversions on the 16th SCLK falling edge. The devices enter the power-down state immediately after
30
Copyright
2011, Texas Instruments Incorporated
Product Folder Link(s): ADS7945 ADS7946
相關(guān)PDF資料
PDF描述
ADS7953SBRHBT 16-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PQCC32
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ADS803E 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
ADS8342IBPFBTG4 4-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PQFP48
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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ADS7947 制造商:TI 制造商全稱:Texas Instruments 功能描述:12/10/8-Bit 2MSPS, Dual-Channel Unipolar Pseudo-Differential Ultralow-Power SAR Analog-to-Digital Converters