參數(shù)資料
型號(hào): ADS7945SRTER
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 2-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PQCC16
封裝: GREEN, PLASTIC, QFN-16
文件頁(yè)數(shù): 22/49頁(yè)
文件大?。?/td> 1322K
代理商: ADS7945SRTER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCLK
CS
D13
SDO
SampleN
SampleN+1
t
ACQ
t
CONV
DataFromSampleN - 1
D12
D11
D10
D9
D8
D7
D6
D4
D3
D2
D1
D0
1
2
11
12
16
17
23
24
25
26
27
28
29
30
SCLK
CS
SDO
SampleN
SampleN+1
t
ACQ
t
CONV
1/
SAMPLE
f
DataFromSampleN
31
32
D13
18
D12
D7
D6
D5
D4
D3
D2
D1
D0
SBAS539B
– JUNE 2011 – REVISED SEPTEMBER 2011
DEVICE OPERATION
The ADS7945/6 operate with either a 16-clock frame or 32-clock frame for ease of interfacing with the host
processor.
16-CLOCK FRAME
Figure 81 shows the devices operating in 16-clock mode. This mode is the fastest mode for device operation. In
this mode, the devices output data from previous conversions while converting the recently sampled signal.
As shown in Figure 81, the ADS7945/6 start acquisition of the analog input from the 16th falling edge of SCLK.
The device samples the input signal on the CS falling edge. SDO comes out of 3-state and the device outputs
the MSB on the CS falling edge. The device outputs the next lower SDO bits on every SCLK falling edge after it
has first seen the SCLK rising edge. The data correspond to the sample and conversion completed in the
previous frame. During a CS low period, the device converts the recently sampled signal. It uses SCLK for
conversions. Conversion is complete on the 16th SCLK falling edge. CS can be high at any time after the 16th
SCLK falling edge (see the Parameter Measurement Information for more details). The CS rising edge after the
16th SCLK falling edge and before the 29th SCLK falling edge keeps the device in the 16-clock data frame. The
device output goes to 3-state when CS is high. It is also permissible to stop SCLK after the device has seen the
16th SCLK falling edge.
Figure 81. ADS7945/6 Operating in 16-Clock Mode without Power-Down (PDEN = 0)
32-CLOCK FRAME
Figure 82 shows the devices operating in 32-clock mode. In this mode, the devices convert and output the data
from the most recent sample before taking the next sample.
Figure 82. ADS7945/6 Operation in 32-Clock Frame without Power-Down (PDEN = 0)
Copyright
2011, Texas Instruments Incorporated
29
Product Folder Link(s): ADS7945 ADS7946
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