參數(shù)資料
型號(hào): ADS1234IPWG4
廠商: Texas Instruments
文件頁(yè)數(shù): 13/39頁(yè)
文件大?。?/td> 0K
描述: IC ADC 24BIT BRDG SENSOR 28TSSOP
產(chǎn)品培訓(xùn)模塊: Data Converter Basics
視頻文件: Nuts and Bolts of the Delta-Sigma Converter
標(biāo)準(zhǔn)包裝: 50
位數(shù): 24
采樣率(每秒): 10,80
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 4.3mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 28-TSSOP
包裝: 管件
輸入數(shù)目和類型: 4 個(gè)單端,單極;2 個(gè)差分,雙極
www.ti.com
OFFSET CALIBRATION
23
DRDY/DOUT
SCLK
1
24
t
8
25
26
23
22
21
0
Data Ready After Calibration
Calibration Begins
SBAS350F – JUNE 2005 – REVISED FEBRUARY 2008
When the calibration is completed, DRDY/DOUT
goes low, indicating that new data are ready. The
Offset calibration can be initiated at any time to
analog input pins are disconnected within the ADC
remove the ADS1232/4 inherited offset error. To
and the appropriate signal is applied internally to
initiate offset calibration, apply at least two additional
perform the calibration. The first conversion after a
SCLKs after retrieving 24 bits of data. Figure 36
calibration is fully settled and valid for use. The offset
shows the timing pattern. The 25th SCLK will send
calibration takes exactly the same time as specified in
DRDY/DOUT high. The falling edge of the 26th SCLK
(t8) right after the falling edge of the 26th SCLK.
will begin the calibration cycle. Additional SCLK
pulses may be sent after the 26th SCLK; however,
activity on SCLK should be minimized during offset
calibration for best results.
Figure 36. Offset-Calibration Timing
SYMBOL
DESCRIPTION
MIN
MAX
UNITS
SPEED = 1
101.28
101.29
ms
t8
(1)
First data ready after calibration
SPEED = 0
801.02
801.03
ms
(1)
Values given for fCLK = 4.9152MHz. For different fCLK frequencies, scale proportional to CLK period. Expect a ±3% variation when an
internal oscillator is used.
20
Copyright 2005–2008, Texas Instruments Incorporated
Product Folder Link(s): ADS1232 ADS1234
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