參數(shù)資料
型號(hào): ADS1203
英文描述: MOTOR CONTROL CURRENT MEASUREMENT
中文描述: 電機(jī)控制電流測量
文件頁數(shù): 16/24頁
文件大小: 276K
代理商: ADS1203
SBAS318 JUNE 2004
www.ti.com
16
Mode 0
In mode 0, the internal RC oscillator is running. The data
is provided at the MDAT output pin, and the modulator
clock at the MCLK pin. The data is changing at the
falling edge of MCLK; therefore, it can safely be strobed
with the rising edge. See Figure 1 on page 6.
Mode 1
In mode 1, the internal RC oscillator is running. The data
is provided at the MDAT output pin. The MCLK pin
provides the half modulator clock. The data must be
strobed at both the rising and falling edges of MCLK.
The data at MDAT is changing in the middle, between
the rising and falling edge. In this mode the frequency
of both MCLK and MDAT is only 5MHz. See Figure 2 on
page 6.
Mode 2
In mode 2, the internal RC oscillator is running. The data
is Manchester encoded and is provided at the MDAT
pin. The MCLK output is set to low. There is no clock
output provided in this mode. The Manchester coding
allows the data transfer with only a single line. See
Figure 3 on page 7.
Mode 3
In mode 3, the internal RC oscillator is disabled. The
system clock must be provided externally at the input
MCLK. The system clock must have twice the
frequency of the chosen modulator clock. The data is
provided at the MDAT output pin. Since the modulator
runs with the half system clock, the data changes at
every other falling edge of the external clock. The data
can safely be strobed at every other rising edge of
MCLK. This mode allows synchronous operation to any
digital system or the use of clocks different from 10MHz.
See Figure 4 on page 7.
FILTER USAGE
The modulator generates only a bitstream, which does
not output a digital word like an analog-to-digital
converter (ADC). In order to output a digital word
equivalent to the analog input voltage, the bitstream
must be processed by a digital filter.
A very simple filter built with minimal effort and
hardware is the sinc
3
filter:
H(z)
1
z
OSR
z
1
1
3
This filter provides the best output performance at the
lowest hardware size (for example, count of digital
gates). For oversampling ratios in the range of 16 to
256, this is a good choice. All the characterizations in
the data sheet are also done using a sinc
3
filter with an
oversampling ratio of OSR = 256 and an output word
width of 16 bits.
In a sinc
3
filter response (shown in Figure 9 and
Figure 10), the location of the first notch occurs at the
frequency of output data rate f
DATA
= f
CLK
/OSR. The
–3dB point is located at half the Nyquist frequency or
f
DATA
/4. For some applications, it may be necessary to
use another filter type for better frequency response.
This performance can be improved, for example, by a
cascaded filter structure. The first decimation stage can
be a sinc
3
filter with a low OSR and the second stage
a high-order filter.
0
10
20
30
40
50
60
70
80
G
Frequency (kHz)
0
200
400
600
800
1000
1200
1400
1600
OSR = 32
f
DATA
= 10MHz/32 = 312.5kHz
3dB: 81.9kHz
Figure 9. Frequency Response of Sinc
3
Filter
30k
25k
20k
15k
10k
5k
0
O
Number of Output Clocks
0
5
10
15
20
25
30
35
40
OSR = 32
FSR = 32768
ENOB = 9.9 Bits
Settling Time =
3
×
1/f
DATA
= 9.6
μ
s
Figure 10. Pulse Response of Sinc
3
Filter
(f
MOD
= 10MHz)
(2)
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