參數(shù)資料
型號: ADS1203
英文描述: MOTOR CONTROL CURRENT MEASUREMENT
中文描述: 電機(jī)控制電流測量
文件頁數(shù): 15/24頁
文件大小: 276K
代理商: ADS1203
SBAS318 JUNE 2004
www.ti.com
15
DIGITAL OUTPUT
A differential input signal of 0V will ideally produce a
stream of ones and zeros that are high 50% of the time
and low 50% of the time. A differential input of +256mV
will produce a stream of ones and zeros that are high
80% of the time. A differential input of –256mV will
produce a stream of ones and zeros that are high 20%
of the time. The input voltage versus the output
modulator signal is shown in Figure 8.
DIGITAL INTERFACE
INTRODUCTION
The analog signal that is connected to the input of the
delta-sigma modulator is converted using the clock
signal applied to the modulator. The result of the
conversion, or modulation, is the output signal DATA
from the delta-sigma modulator. In most applications
where a direct connection is realized between the
delta-sigma modulator and an ASIC, FPGA, DSP, or
μ
C
(each with an implemented filter), the two standard
signals (MCLK and MDAT) are provided from the
modulator. To reduce the wiring (for example, for
galvanic isolation), a single line is preferred. Therefore,
in mode 2, the data stream is Manchester encoded.
MODES OF OPERATION
The system clock of the ADS1203 is 20MHz by default.
The system clock can be provided either from the
internal 20MHz RC oscillator or from an external clock
source. For this purpose, the MCLK pin is bidirectional
and controlled by the mode setting.
The system clock is divided by 2 for the modulator
clock. Therefore, the default clock frequency of the
modulator is 10MHz. With a possible external clock
range of 1MHz to 32MHz, the modulator operates
between 500kHz and 16MHz.
The four modes of operation for the digital data interface
are shown in Table 1.
Modulator Output
Analog Input
+FS (Analog Input)
FS (Analog Input)
Figure 8. Analog Input vs Modulator Output of the ADS1203
Table 1. Digital Data Interface Modes of Operation
MODE
DEFINITION
M1
M0
0
Internal clock, synchronous data output
Low
Low
1
Internal clock, synchronous data output, half output clock frequency
Low
High
2
Internal clock, Manchester encoded data output
High
Low
3
External clock, synchronous data output
High
High
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