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參數(shù)資料
| 型號： | ADS1000A1IDBVTG4 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | LOW POWER, 12-Bit ANALOG-TO-DIGITAL CONVERTER with I2C⑩ INTERFACE |
| 中文描述： | 低功耗，12位模擬數(shù)字轉(zhuǎn)換接口的I2C⑩ |
| 文件頁數(shù)： | 8/17頁 |
| 文件大?。?/td> | 240K |
| 代理商： | ADS1000A1IDBVTG4 |
www.ti.com
I
2
C GENERAL CALL
REGISTERS
OUTPUT REGISTER
I
2
C DATA RATES
The I
2
C bus operates in one of three speed modes:
Standard
, which allows a clock frequency of up to
100kHz;
Fast
, which allows a clock frequency of up
to 400kHz; and
High-speed
mode (also called Hs
mode), which allows a clock frequency of up to
3.4MHz. The ADS1000 is fully compatible with all
three modes.
ADS1000
SBAS357–SEPTEMBER 2006
ADS1000
High-speed mode must be activated. To activate
High-speed mode, send a special address byte of
00001XXX following the start condition, where the
XXX
bits are unique to the Hs-capable master. This
byte is called the
Hs master code
. (Note that this is
different from normal address bytes; the low bit does
not indicate read/write status.) The ADS1000 will not
acknowledge this byte; the I
2
C specification prohibits
acknowledgment
of
the
receiving a master code, the ADS1000 will switch on
its High-speed mode filters, and will communicate at
up to 3.4MHz. The ADS1000 switches out of Hs
mode with the next stop condition.
in
Standard
or
Fast
modes,
but
ADS1000 I
2
C ADDRESSES
The ADS1000 I
2
C address is either 1001000 or
1001001, set at the factory. The address is identified
with an A0 or an A1 within the orderable name.
The two different I
2
C variants are also marked
differently. Devices with an I
2
C address of 1001000
have packages marked
BD0
, while devices with an
I
2
C address of 1001001 are marked with
BD1
. See
the
Package/Ordering
Information
complete listing of the ADS1000 I
2
C addresses and
tape and reel size.
Hs
master
code.
On
Table
for
a
For more information on High-speed mode, consult
the I
2
C specification.
The ADS1000 responds to General Call Reset,
which is an address byte of 00h followed by a data
byte of 06h. The ADS1000 acknowledges both bytes.
The ADS1000 has two registers that are accessible
via its I
2
C port. The output register contains the
result of the last conversion; the configuration
register allows
users
to
operating mode and query the status of the device.
On receiving a General Call Reset, the ADS1000
performs a full internal reset, just as though it had
been powered off and then on. If a conversion is in
process, it is interrupted; the output register is set to
zero, and the configuration register returns to its
default setting.
change
the
ADS1000
The ADS1000 always acknowledges the General
Call
address
byte
of
acknowledge any General Call data bytes other than
04h or 06h.
The 16-bit output register contains the result of the
last conversion in binary two’s complement format.
Since the port yields 12 bits of data, the ADS1000
outputs right-justified and sign-extended codes. This
output format makes it possible to perform averaging
using a 16-bit accumulator.
00h,
but
it
does
not
Following reset or power-up, the output register is
cleared to '0'; it remains zero until the first conversion
is
completed.
Therefore,
ADS1000 just after reset or power-up, the output
register will read '0'.
if
a
user
reads
the
The output register format is shown in
Table 2
.
No special action needs to be taken to use the
Table 2. OUTPUT REGISTER
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NAME
D15
(1)
D14
(1)
D13
(1)
D12
(1)
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
(1)
D15–D12 are sign extensions of 12-bit data.
8
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