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參數(shù)資料
| 型號： | ADS-CCD1202MM |
| 廠商： | MURATA POWER SOLUTIONS INC |
| 元件分類： | ADC |
| 中文描述： | 1-CH 12-BIT FLASH METHOD ADC, PARALLEL ACCESS, CDIP24 |
| 封裝： | DDIP-24 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大小： | 724K |
| 代理商： | ADS-CCD1202MM |
ADS -CCD1202
TIMING
The ADSCCD-1202 is an edge triggered device. A conversion
is initiated by the rising edge of the start convert pulse and no
additional external timing signals are required. The device does
not employ "pipeline" delays to increase its throughput rate. It
does not require multiple start convert pulses to bring valid
digital data to its output pins.
Figure 5.
ADS-CCD1202 Evaluation Board Schematic
32
30
28
26
24
22
20
33
6
8
10
12
14
16
18
31
27
29
23
25
19
21
3
5
7
9
11
13
15
P2
17
1
2
4
34
5%
200K
R3
0.1%
1.98K
R4
–
+
U6
2
3
4
6
7
OP-77
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
1G
2G
2A4
2A3
2A2
2A1
1A4
1A3
1A2
1A1
U3
2
4
6
8
11
13
15
17
19
10
20
18
16
14
12
9
7
5
3
1
74LS240
.1%
2K
R5
0.1%
R8
P3
P4
74LS86
U4
9
10
8
74LS86
U4
12
13
11
0.1MF
C7
0.1MF
C5
0.1MF
C3
0.1MF
C17
0.1MF
C16
0.1MF
C1
0.1MF
C15
15pF
C2
0.1MF
C10
0.1MF
C12
0.1MF
C13
2.2MF
C6
+
2.2MF
7
C4
+
2.2MF
+
C9
2.2MF
C8
+
2.2MF
C11
+
2.2MF
+
C14
+5V
+5V
+5V
+5V
+15V
+15V
+15V
+15V
-15V
-15V
-15V
-15V
+5V
P1
1
3
2
4
5
6
8
7
10
9
12 11
14 13
16 15
18 17
20 19
22 21
24 23
26
25
20K
R2
50
R1
74LS86
U4
4
5
6
74LS86
U4
1
2
3
7
14
B1
B2
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
EOC
+5V
DGND
ST. CONV
AGND
INPUT
+10VREF
+15V
AGND
-15V
U1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SG1
–
+
U5
2
3
4
6
AD845
0.1%
10K
R7
0.1%
2K
R6
-15V
2.2
C22
+
0.1MF
+15V
2.2MF
C19
+
0.1MF
C20
Y1
1
7
8
14
XTAL
J3
J5
J4
J2
0.1MF
C21
J1
+5V
C18
SG2
SG3
2.2MF
C24
+
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
1G
2G
2A4
2A3
2A2
2A1
1A4
1A3
1A2
1A1
U2
2
4
6
8
11
13
15
17
19
10
20
18
16
14
12
9
7
5
3
1
74LS240
B13
B11
B12
B10
B9
B6
B5
B4
B3
B14
B1
B2
B8
B7
SEE NOTE 1
ST.CONV.
ENABLE
MSB
LSB
EOC
COG
ADJ
GAIN
ADJ
OFFSET
CONVERT
START
INPUT
ANALOG
1. FOR ADS-BCCD1201 Y1 IS 2MHZ
NOTES:
ADS-CCD1201/1202
Figure 4. ADS-CCD1202 Timing Diagram
START
CONVERT
OUTPUT DATA
INTERNAL S/H
N
DATA (N-1) VALID
200ns typ.
Acquisition Time
10ns typ.
DATA N VALID
425ns min.
Note: Scale is approximately 25ns per division.
EOC
30ns typ.
Conversion Time
360ns ±20ns
INVALID
DATA
75ns max.
70ns ±10ns
310ns typ.
35ns max.
Hold
N+1
190ns typ.
5.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADS-CCD1202MM-QL | 制造商:Murata Power Solutions 功能描述:Analog to Digital Converter |
| ADS-COR-SDR1 | 制造商:Avnet Design Services - Custom 功能描述:ADRAM BINARY CORE LICENSE - Virtual or Non-Physical Inventory (Software & Literature) |
| ADS-COR-SDRSPD1 | 制造商:Avnet Design Services - Custom 功能描述:SDRAM W/SPD BINARY CORE LICENSE - Virtual or Non-Physical Inventory (Software & Literature) |
| ADSCPA | 制造商:Pentair Technical Products / Hoffman 功能描述:Platform Assembly 制造商:PENTAIR TECNICAL PRODCUTS 功能描述:Platform Assembly |
| A-DSCR/09/FZ | 制造商:Assmann 功能描述:9w male crimp contact housing |
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