參數(shù)資料
型號(hào)： ADP5041ACPZ-1-R7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 27/40頁(yè)
文件大?。?/td> 3581K
描述： IC REG TRPL BCK/LINEAR 20-LFCSP
標(biāo)準(zhǔn)包裝： 1
拓?fù)洌?/td> 降壓（降壓）同步（1），線性（LDO）（2）
功能： 任何功能
輸出數(shù)： 3
頻率 - 開(kāi)關(guān)： 3MHz
電壓/電流 - 輸出 1： 0.8 V ~ 3.8 V，1.2A
電壓/電流 - 輸出 2： 0.8 V ~ 5.2 V，300mA
電壓/電流 - 輸出 3： 0.8 V ~ 5.2 V，300mA
帶 LED 驅(qū)動(dòng)器： 無(wú)
帶監(jiān)控器： 是
帶序列發(fā)生器： 無(wú)
電源電壓： 2.3 V ~ 5.5 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 20-WFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 20-LFCSP-WQ（4x4）
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： ADP5041ACPZ-1-R7DKR
Data Sheet
ADP5041
 
Rev. 0 | Page 27 of 40
Thermal Protection
In the event that the junction temperature rises above 150癈,
the thermal shutdown circuit turns off the buck and the LDOs.
Extreme junction temperatures can be the result of high current
operation, poor circuit board design, or high ambient temperature.
A 20癈 hysteresis is included in the thermal shutdown circuit so
that when thermal shutdown occurs, the buck and the LDOs do
not return to normal operation until the on-chip temperature
drops below 130癈. When coming out of thermal shutdown, all
regulators start with soft start control.
Undervoltage Lockout
To protect against battery discharge, undervoltage lockout
(UVLO) circuitry is integrated in the ADP5041. If the input
voltage on AVIN drops below a typical 2.15 V UVLO threshold,
all channels shut down. In the buck channel, both the power
switch and the synchronous rectifier turn off. When the voltage
on AVIN rises above the UVLO threshold, the part is enabled
once more.
Alternatively, the user can select device models with a UVLO
set at a higher level, suitable for 5 V applications. For these
models, the device reaches the turn-off threshold when the
input supply drops to 3.65 V typical.
Enable/Shutdown
The ADP5041 has individual control pins for each regulator.
A logic level high applied to the ENx pin activates a regulator,
whereas a logic level low turns off a regulator.
Active Pull-Down
The ADP5041 can be ordered with the active pull-down option
enabled. The pull-down resistors are connected between each
regulator output and AGND. The pull-downs are enabled, when
the regulators are turned off. The typical value of the pull-down
resistor is 600 ?for the LDOs and 85 ?for the buck.
BUCK SECTION
The buck uses a fixed frequency and high speed current mode
architecture. The buck operates with an input voltage of 2.3 V
to 5.5 V.
The buck output voltage is set through external resistor
dividers, shown in Figure 102. VOUT1 must be connected to
the output capacitor. V
FB1
 is internally set to 0.5 V. The output
voltage can be set from 0.8 V to 3.8 V.
 
BUCK
VOUT1
VOUT1
SW
IN1
FB1
AGND
C5
10礔
R1
R2
L1  1礖
 
Figure 102. Buck External Output Voltage Setting
Control Scheme
The buck operates with a fixed frequency, current mode PWM
control architecture at medium to high loads for high efficiency,
but operation shifts to a power save mode (PSM) control
scheme at light loads to lower the regulation power losses.
When operating in fixed frequency PWM mode, the duty cycle
of the integrated switches is adjusted and regulates the output
voltage. When operating in PSM at light loads, the output
voltage is controlled in a hysteretic manner, with higher output
voltage ripple. During part of this time, the converter is able to
stop switching and enters an idle mode, which improves
conversion efficiency.
PWM Mode
In PWM mode, the buck operates at a fixed frequency of 3 MHz,
set by an internal oscillator. At the start of each oscillator cycle,
the PFET switch is turned on, sending a positive voltage across
the inductor. Current in the inductor increases until the current
sense signal crosses the peak inductor current threshold that
turns off the PFET switch and turns on the NFET synchronous
rectifier. This sends a negative voltage across the inductor,
causing the inductor current to decrease. The synchronous
rectifier stays on for the rest of the cycle. The buck regulates the
output voltage by adjusting the peak inductor current threshold.
Power Save Mode (PSM)
The buck smoothly transitions to PSM operation when the load
current decreases below the PSM current threshold. When the
buck enters power-save mode, an offset is introduced in the
PWM regulation level, which makes the output voltage rise.
When the output voltage reaches a level that is approximately
1.5% above the PWM regulation level, PWM operation is
turned off. At this point, both power switches are off, and the
buck enters an idle mode. The output capacitor discharges until
the output voltage falls to the PWM regulation voltage, at which
point the device drives the inductor to make the output voltage
rise again to the upper threshold. This process is repeated while
the load current is below the PSM current threshold.
The ADP5041 has a dedicated MODE pin controlling the PSM
and PWM operation. A high logic level applied to the MODE
pin forces the buck to operate in PWM mode. A logic level low
sets the buck to operate in auto PSM/PWM.
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