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參數(shù)資料
| 型號(hào)： | ADP5041ACPZ-1-R7 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 26/40頁(yè) |
| 文件大?。?/td> | 3581K |
| 描述： | IC REG TRPL BCK/LINEAR 20-LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 拓?fù)洌?/td> | 降壓（降壓）同步（1），線性（LDO）（2） |
| 功能： | 任何功能 |
| 輸出數(shù)： | 3 |
| 頻率 - 開關(guān)： | 3MHz |
| 電壓/電流 - 輸出 1： | 0.8 V ~ 3.8 V，1.2A |
| 電壓/電流 - 輸出 2： | 0.8 V ~ 5.2 V，300mA |
| 電壓/電流 - 輸出 3： | 0.8 V ~ 5.2 V，300mA |
| 帶 LED 驅(qū)動(dòng)器： | 無(wú) |
| 帶監(jiān)控器： | 是 |
| 帶序列發(fā)生器： | 無(wú) |
| 電源電壓： | 2.3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-WFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 20-LFCSP-WQ（4x4） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | ADP5041ACPZ-1-R7DKR |
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ADP5041
Data Sheet
Rev. 0 | Page 26 of 40
THEORY OF OPERATION
PWM/
PSM
CONTROL
BUCK1
DRIVER
AND
ANTISHOOT
THROUGH
RESET
GENERATOR
DEBOUNCE
VDDA
VDDA
PSM
COMP
LOW
CURRENT
I
LIMIT
ADP5041
VOUT1 FB1
VTHR
ENWD
VIN1
AVIN
SW
GND
EN1
ENBK
ENLDO1
ENLDO2
ODE
MODE
EN2
EN3
SEL
OPMODE_FUSES
VIN2
FB2 AGND VOUT2 VIN3
ENLDO1
600&
ENBK
ENLDO2
600&
MR
VDDA
52k&
WDI
VOUT3
FB3
OSCILLATOR
THERMAL
SHUTDOWN
V
REF
WATCHDOG
DETECTOR
nRSTO
VDDA
PWM
COMP
GM ERROR
AMP
85&
SOFT START
SYSTEM
UNDERVOLTAGE
LOCK OUT
ENABLE
AND MODE
CONTROL
LDO1
CONTROL
LDO2
CONTROL
Figure 101. Functional Block Diagram
POWER MANAGEMENT UNIT
The ADP5041 is a micro power management unit (micro PMU)
combing one step-down (buck) dc-to-dc regulator, two low
dropout linear regulators (LDOs), and a supervisory circuit, with
watchdog, for processor control. The high switching frequency and
tiny 20-pin LFCSP package allow for a small power management
solution.
The regulators are activated by a logic level high applied to the
respective EN pin. The EN1 pin controls the buck regulator, the
EN2 pin controls LDO1, and the EN3 pin controls LDO2.
Other features available on this device are the MODE pin to
control the buck switching operation and a push-button reset
input.
The regulator output voltages and the reset threshold are set
through external resistor dividers.
When a regulator is turned on, the output voltage ramp is
controlled through a soft start circuit to avoid a large inrush
current due to the discharged output capacitors.
The buck regulator can operate in forced PWM mode if the
MODE pin is at a logic high level. In forced PWM mode, the
switching frequency of the buck is always constant and does not
change with the load current. If the MODE pin is at a logic low
level, the switching regulator operates in auto PWM/PSM mode.
In this mode, the regulator operates at fixed PWM frequency
when the load current is above the power save current threshold.
When the load current falls below the power saving current
threshold, the regulator enters power saving mode, where the
switching occurs in bursts. The burst repetition rate is a
function of the current load and the output capacitor value.
This operating mode reduces the switching and quiescent
current losses.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADP5041CP-1-EVALZ | 功能描述:ADP5041 - DC/DC, Step Down with LDO 3, Non-Isolated Outputs Evaluation Board 制造商:analog devices inc. 系列:- 零件狀態(tài):有效 主要用途:DC/DC，LDO 步降 輸出和類型:3，非隔離 功率 - 輸出:- 電壓 - 輸出:- 電流 - 輸出:1.2A，300mA，300mA 電壓 - 輸入:2.3 V ~ 5.5 V 穩(wěn)壓器拓?fù)?降壓 頻率 - 開關(guān):3MHz 板類型:完全填充 所含物品:板 使用的 IC/零件:ADP5041 標(biāo)準(zhǔn)包裝:1 |
| ADP5042 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Micro PMU with 0.8 A Buck, Two 300 mA LDOs Supervisory, Watchdog and Manual Reset |
| ADP5042ACPZ-1 | 制造商:Analog Devices 功能描述:PMU 2 LDO DUAL BUCK 20LFCSP 制造商:Analog Devices 功能描述:PMU, 2 LDO, DUAL BUCK, 20LFCSP |
| ADP5042ACPZ-1-R7 | 功能描述:IC REG TRPL BCK/LINEAR 20LFCSP RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - 線性 + 切換式 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 拓?fù)?降壓（降壓）同步（3），線性（LDO）（2） 功能:任何功能 輸出數(shù):5 頻率 - 開關(guān):300kHz 電壓/電流 - 輸出 1:控制器 電壓/電流 - 輸出 2:控制器 電壓/電流 - 輸出 3:控制器 帶 LED 驅(qū)動(dòng)器:無(wú) 帶監(jiān)控器:無(wú) 帶序列發(fā)生器:是 電源電壓:5.6 V ~ 24 V 工作溫度:-40°C ~ 85°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| ADP5042ACPZ-2 | 制造商:Analog Devices 功能描述:PMU 2 LDO DUAL BUCK 20LFCSP 制造商:Analog Devices 功能描述:PMU, 2 LDO, DUAL BUCK, 20LFCSP |
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