參數(shù)資料
型號(hào)： ADNS-5020-EN
廠商： Avago Technologies Ltd.
英文描述： Optical Mouse Sensor
中文描述： 光學(xué)鼠標(biāo)傳感器
文件頁(yè)數(shù)： 14/24頁(yè)
文件大?。?/td> 278K
代理商： ADNS-5020-EN
14
Notes on Power-up and Reset
The ADNS-5020-EN does not perform an internal power
up self-reset; the NRESET pin must be asserted low every
time power is applied. There are two ways to reset the
chip, either assert low NRESET pin or by writing 0x5a
to register 0x3a. A full reset will thus be executed. Any
register settings must then be reloaded.
Burst Mode Operation
Burst mode is a special serial port operation mode that
may be used to reduce the serial transaction time for a
motion read. The speed improvement is achieved by con-
tinuous data clocking to or from multiple registers without
the need to specify the register address, and by not
requiring the normal delay period between data bytes.
Burst mode is activated by reading the Motion_Burst
register. The ADNS-5020-EN will respond with the
contents of the Delta_X, Delta_Y, SQUAL, Shutter_
Upper, Shutter_Lower, Maximum_Pixel and Pixel_Sum
registers in that order. The burst transaction can
be terminated anywhere in the sequence after the
Delta_X value by bringing the NCS pin high. After
sending the register address, the micro-controller must
wait t
SRAD
and then begin reading data. All data bits can
be read with no delay between bytes by driving SCLK
at the normal rate. The data are latched into the output
buffer after the last address bit is received. After the burst
transmission is complete, the micro-controller must raise
the NCS line for at least t
BEXIT
to terminate burst mode. The
serial port is not available for use until it is reset with NCS,
even for a second burst transmission.
Avago Technologies highly recommends the usage of burst
mode operation in optical mouse sensor design applica-
tions.
Motion Burst Timing
MOTION_BURST REGISTER ADDRESS
READ FIRST BYTE
FIRST READ OPERATION
READ SECOND BYTE
READ THIRD BYTE
SCLK
t
SRAD
Notes on Power Down
The ADNS-5020-EN can be set in Power Down mode by
setting bit 1 of register 0x0d. In addition, the SPI port
should not be accessed during power down. (Other
ICs on the same SPI bus can be accessed, as long as the
sensor’s NCS pin is not asserted.) The table below shows
the state of various pins during power down. There are 2
ways to exit power down, either assert low NRESET pin or
by writing 0x5a to Register 0x3a. A full reset will thus be
executed. Wait tWAKEUP before accessing the SPI port.
Any register settings must then be reloaded.
Pin
NRESET
NCS
SDIO
SCLK
XY_LED
Power Down Active
Functional
Functional*
Functional*
Functional*
Low current
* NCS pin must be held to 1(high) if SPI bus is shared with other
devices. It can be in either state if the sensor is the only device in
addition to the controller microprocessor.
Note:
There is long wakeup time from power down. The feature should not
be used for power management during normal mouse motion.
During power-up there will be a period of time after the
power supply is high but before any clocks are available.
The table below shows the state of the various pins
during power-up and reset.
State of Signal Pins After VDD is Valid
Pin
During Reset
NCS
Ignored
SDIO
Ignored
SCLK
Ignored
XY_LED
Hi-Z
After Reset
Functional
Depends on NCS
Depends on NCS
Functional
相關(guān)PDF資料
PDF描述
ADNS-5030 Low Power Optical Mouse Sensor
ADNS-5100 Solid-State Optical Mouse Lens
ADNS-5100-001 Solid-State Optical Mouse Lens
ADPDC2BB4AW General Purpose Snap-acting Switches
ADGGF3B14AC General Purpose Snap-acting Switches
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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