參數(shù)資料
型號: ADN4692EBRZ
廠商: Analog Devices Inc
文件頁數(shù): 8/20頁
文件大?。?/td> 0K
描述: IC INTERFACE TXRX
標準包裝: 56
系列: *
ADN4690E/ADN4692E
Data Sheet
Rev. 0 | Page 16 of 20
APPLICATIONS INFORMATION
M-LVDS extends the low power, high speed, differential signal-
ing of LVDS (low voltage differential signaling) to multipoint
systems where multiple nodes are connected over short distances
in a bus topology network.
With M-LVDS, a transmitting node drives a differential signal
across a transmission medium such as a twisted pair cable. The
transmitted differential signal allows other receiving nodes
connected along the bus to detect a differential voltage that can
then be converted back into a single-ended logic signal by the
receiver.
The communication line is typically terminated at both ends
by resistors (RT), the value of which is chosen to match the
characteristic impedance of the medium (typically 100 Ω).
For half-duplex multipoint applications such as the one shown
in Figure 36, only one driver can be enabled at any time. Full-
duplex nodes allow a master slave topology, as shown in Figure 37.
In this configuration, a master node can concurrently send and
receive data to/from slave nodes. At any time, only one slave
node can have its driver enabled to concurrently transmit data
back to the master node.
RO
NOTES
1. MAXIMUM NUMBER OF NODES: 32.
2. RT IS EQUAL TO THE CHARACTERISTIC IMPEDANCE OF THE CABLE USED.
RE
AB
RT
ADN4690E
DE
DI
RO RE
AB
ADN4690E
DE
DI
RO RE
AB
ADN4690E
DE
DI
RO RE
AB
ADN4690E
DE
DI
104
71-
035
Figure 36. ADN4690E Typical Half-Duplex M-LVDS Network (Type 1 Receivers with Hysteresis)
RO
NOTES
1. MAXIMUM NUMBER OF NODES: 32.
2. RT IS EQUAL TO THE CHARACTERISTIC IMPEDANCE OF THE CABLE USED.
RE
AB Z Y
MASTER
SLAVE
RT
ADN4692E
DE
DI
RO RE DE
DI
RO RE DE
DI
AB Z Y
ADN4692E
AB Z Y
ADN4692E
AB Z Y
ADN4692E
RT
RO RE DE
DI
10471
-036
R
D
R
D
R
D
R
D
Figure 37. ADN4692E Typical Full-Duplex M-LVDS Master-Slave Network (Type 1 Receivers with Hysteresis)
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相關代理商/技術參數(shù)
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