
3.3 V, 100 Mbps, Half- and Full-Duplex,
High Speed M-LVDS Transceivers
Data Sheet
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringementsof patentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2012 Analog Devices, Inc. All rights reserved.
FEATURES
Multipoint LVDS transceivers (low voltage differential
signaling driver and receiver pairs)
Switching rates: 100 Mbps (50 MHz)
Supported bus loads: 30 Ω to 55 Ω
Conforms to TIA/EIA-899 standard for M-LVDS
Glitch-free power-up/power-down on M-LVDS bus
Controlled transition times on driver output
Common-mode range: –1 V to +3.4 V, allowing
communication with 2 V of ground noise
Driver outputs high-Z when disabled or powered off
Enhanced ESD protection on bus pins
±15 kV HBM (human body model), air discharge
±8 kV HBM (human body model), contact discharge
±10 kV IEC 61000-4-2, air discharge
±8 kV IEC 61000-4-2, contact discharge
Operating temperature range: 40°C to +85°C
SOIC packages
APPLICATIONS
Backplane and cable multipoint data transmission
Multipoint clock distribution
Low power, high speed alternative to shorter RS-485 links
Networking routers and switches
Wireless base station infrastructure
FUNCTIONAL BLOCK DIAGRAMS
ADN4690E
VCC
GND
RO
R
D
RE
DE
A
B
DI
10471-
001
Figure 1.
ADN4692E
VCC
GND
RO
R
D
RE
DE
DI
10471-
102
A
B
Z
Y
Figure 2.
GENERAL DESCRIPTION
ferential signaling (M-LVDS) transceivers (driver and receiver
pairs) that can operate at up to 100 Mbps (50 MHz). To improve
the integrity of the output signal and minimize reflections, slew
rate control is implemented on the driver outputs. The receivers
detect the bus state with a differential input of as little as 50 mV
over a common-mode voltage range of 1 V to +3.4 V. ESD
protection of up to ±15 kV is implemented on the bus pins.
standard for M-LVDS and complement TIA/EIA-644 LVDS
devices with additional multipoint capabilities. The driver allows
bus loads of as little as 30 Ω on a multipoint bus topology, and
driver output transition times are controlled to minimize
reflections. Up to 32 nodes can be connected to the bus.
designed to have 25 mV of hysteresis on the differential input
voltage, so that slow-changing signals or a loss of input does not
lead to output oscillations.
configurations in an 8-lead SOIC package (the
ADN4690E)or as full-duplex configurations in a 14-lead SOIC package
(the
ADN4692E). A selection table for the ADN469xE parts
Table 1. ADN469xE Selection Table
Part No.
Receiver
Type
Data
Rate
SOIC
Package
Half-/Full-
Duplex
Type 1
100 Mbps
8-lead
Half
Type 1
100 Mbps
14-lead
Full
Type 2
200 Mbps
8-lead
Half
Type 2
200 Mbps
14-lead
Full