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參數資料
| 型號： | ADN2850BCPZ250-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 16/28頁 |
| 文件大小： | 0K |
| 描述： | IC DGTL RHEO DL 25K 9BIT16LFCSP |
| 產品變化通告： | Metal Edit Change 03/Feb/2012 |
| 標準包裝： | 1,500 |
| 接片： | 1024 |
| 電阻（歐姆）： | 250k |
| 電路數： | 2 |
| 溫度系數： | 標準值 35 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | 4 線 SPI（芯片選擇） |
| 電源電壓： | 3 V ~ 5.5 V，±2.25 V ~ 2.75 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-VQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 16-LFCSP |
| 包裝： | 帶卷 (TR) |
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Data Sheet
ADN2850
Rev. E | Page 23 of 28
where:
IS1 and IS2 are saturation current.
V1, V2 are VBE, base-emitted voltages of the diode connector
transistors.
VT is the thermal voltage, which is equal to k × T/q
(VT = 26 mV @ 25°C)
k is the Boltzmann’s constant, 1.38e-23 Joules/Kelvin.
q is the electron charge, 1.6e-19 coulomb.
T is the temperature in Kelvin.
IPD is the photodiode current.
IREF is the reference current.
Figure 38 shows a conceptual circuit.
LPF
0.75 BIT RATE
TIA
AD623
IN AMP
10nF
CDR
POST
AMP
VT COMPENSATION
ADN2850
LOG
AVERAGE
POWER
W1
B1
B2
VDD
VSS
IPD
IREF
RG
W2
V1
V2
Q1
Q2
°C
PRC
THERMISTOR
DATA
CLOCK
LOG AMP
GND
–5V
(1 + 100k/RG)×(V1 –V2)
02660-
137
Figure 38. Conceptual Incoming Optical Power Monitoring Circuit
The output voltage represents the average incoming optical
power. The output voltage of the log stage does not have to be
accurate from device to device, as the responsivity of the
photodiode will change between devices. An op amp stage is
shown after the log amp stage, which compensates for VT
variation over temperature.
Equation 19 is ideal. If the reference current is 1 mA at room
temperature, characterization shows that there is an additional
30 mV offset between V2 and V1. A curve fit approximation
yields
03
.
0
001
.
0
ln
026
.
0
1
2
PD
I
V
(19)
The offset is caused by the transistors self-heating and the
thermal gradient effect. As seen in Figure 39, the error between
an approximation and the actual performance ranges is less
than 0% to –4% from 0.1 mA to 0.1 μA.
0.30
0.25
0.20
0.15
0.10
0.05
0
12
9
ERROR
6
3
0
–3
–6
0.1
1
10
100
1m
026
60
-138
V
2
–V
1
(V
)
APP
ROXIMAT
ING
E
RROR
(%)
IPD (A)
IREF =1mA
TA = 25°C
DEVICE 1
DEVICE 2
DEVICE 3
CURVE FIT
Figure 39. V2 – V1 Error Versus Input Current.
RESISTANCE SCALING
The ADN2850 offers 25 kΩ or 250 kΩ nominal resistance.
When users need lower resistance but must maintain the
number of adjustment steps, they can parallel multiple devices. For
example, Figure 40 shows a simple scheme of paralleling two
channels of RDACs. To adjust half the resistance linearly per
step, program both RDACs concurrently with the same settings.
B1
W1
W2
B2
0
266
0-
058
Figure 40. Reduce Resistance by Half with Linear Adjustment Characteristics
Figure 40 shows that the digital rheostat change steps linearly.
Alternatively, pseudo log taper adjustment is usually preferred in
applications such as audio control. Figure 41 shows another type
of resistance scaling. In this configuration, the smaller the R2
with respect to RAB, the more the pseudo log taper characteristic
of the circuit behaves.
B1
W1
R
0
2660-
0
60
Figure 41. Resistor Scaling with Pseudo Log Adjustment Characteristics
The equation is approximated as
R
WB
QUIVALENT
1024
200
,
51
200
,
51
E
(17)
Users should also be aware of the need for tolerance matching
as well as for temperature coefficient matching of the components.
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