參數(shù)資料
型號(hào)： ADN2819ACP-CML
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字傳輸電路
英文描述： Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp
中文描述： CLOCK RECOVERY CIRCUIT, QCC48
封裝： 7 X 7 MM, MO-220-VKKD-2, LFCSP-48
文件頁(yè)數(shù)： 19/24頁(yè)
文件大?。?/td> 570K
代理商： ADN2819ACP-CML
ADN2819
CHOOSING AC-COUPLING CAPACITORS
The choice of ac-coupling capacitors at the input (PIN, NIN)
and output (DATAOUTP, DATAOUTN) of the ADN2819 must
be chosen such that the device works properly at the lower
OC-3 and higher OC-48 data rates. When choosing the
capacitors, the time constant formed with the two 50 resistors
in the signal path must be considered. When a large number of
consecutive identical digits (CIDs) are applied, the capacitor
voltage can drop due to baseline wander (see Figure 23), causing
pattern dependent jitter (PDJ).
Rev. B | Page 19 of 24
For the ADN2819 to work robustly at both OC-3 and OC-48, a
minimum capacitor of 1.6 μF to PIN/NIN and 0.1 μF on
DATAOUTP/DATAOUTN should be used. This is based on the
assumption that 1000 CIDs must be tolerated and that the PDJ
should be limited to 0.01 UI p-p.
50
ADN2819
NIN
PIN
50
V
REF
C
IN
C
IN
V2
V1
V2b
V1b
TIA
LIMAMP
CDR
C
OUT
C
OUT
DATAOUTP
DATAOUTN
+
4
3
2
1
V1
V1b
V2
V2b
V
DIFF
V
DIFF
= V2–V2b
VTH = ADN2819 QUANTIZERTHRESHOLD
V
REF
VTH
NOTES
1. DURING DATA PATTERNS WITH HIGH TRANSITION DENSITY, DIFFERENTIAL DC VOLTAGE AT V1 AND V2 IS 0.
2. WHENTHE OUTPUT OFTHE TIA GOESTO CID, V1 AND V1b ARE DRIVENTO DIFFERENT DC LEVELS. V2 AND V2b DISCHARGE TOTHE V
REF
LEVEL,
WHICH EFFECTIVELY INTRODUCES A DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS.
3. WHENTHE BURST OF DATA STARTS AGAIN,THE DIFFERENTIAL DC OFFSET ACROSSTHE AC COUPLING CAPACITORS IS APPLIEDTOTHE INPUT LEVELS,
CAUSING A DC SHIFT INTHE DIFFERENTIAL INPUT. THIS SHIFT IS LARGE ENOUGH SUCHTHAT ONE OFTHE STATES, EITHER HIGH OR LOW DEPENDING ON
THE LEVELS OF V1 AND V1bWHENTHE TIAWENTTO CID, IS CANCELLED OUT. THE QUANTIZERWILL NOT RECOGNIZETHIS AS AVALID STATE.
4. THE DC OFFSET SLOWLY DISCHARGES UNTILTHE DIFFERENTIAL INPUTVOLTAGE EXCEEDSTHE SENSITIVITY OFTHE ADN2819.THE QUANTIZERWILL BE
ABLETO RECOGNIZE BOTH HIGH AND LOW STATES ATTHIS POINT.
0
Figure 25. Example of Baseline Wander
相關(guān)PDF資料
PDF描述
ADN2819ACP-CML-RL Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp
ADN2819ACPZ-CML-RL1 Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp
ADN2819ACPZ-CML1 Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp
ADN2830ACP32-REEL Circular Connector; No. of Contacts:4; Series:LJT06R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:21; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:21-75
ADN2830ACP32-REEL7 Circular Connector; No. of Contacts:4; Series:LJT06R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:21; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:21-75
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADN2819ACP-CML-RL 制造商:Analog Devices 功能描述:CDR 2488.32Mbps/2666.06Mbps SONET/SDH 48-Pin LFCSP EP T/R
ADN2819ACPZ-CML 功能描述:IC CLOCK/DATA RECOVERY 48LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無(wú)/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件
ADN2819ACPZ-CML1 制造商:AD 制造商全稱:Analog Devices 功能描述:Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp
ADN2819ACPZ-CML-RL 功能描述:IC CLOCK/DATA RECOVERY 48LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無(wú)/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件
ADN2819ACPZ-CML-RL1 制造商:AD 制造商全稱:Analog Devices 功能描述:Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*