參數(shù)資料
型號(hào)： ADN2819ACP-CML
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字傳輸電路
英文描述： Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp
中文描述： CLOCK RECOVERY CIRCUIT, QCC48
封裝： 7 X 7 MM, MO-220-VKKD-2, LFCSP-48
文件頁(yè)數(shù)： 13/24頁(yè)
文件大?。?/td> 570K
代理商： ADN2819ACP-CML
ADN2819
The gain of the loop integrator is small for high jitter
frequencies, so larger phase differences are needed to make the
loop control voltage big enough to tune the range of the phase
shifter. Large phase errors at high jitter frequencies cannot be
tolerated. In this region, the gain of the integrator determines
the jitter accommodation. Since the gain of the loop integrator
declines linearly with frequency, jitter accommodation is lower
with higher jitter frequency. At the highest frequencies, the loop
gain is very small and little tuning of the phase shifter can be
expected. In this case, jitter accommodation is determined by
the eye opening of the input data, the static phase error, and the
residual loop jitter generation. The jitter accommodation is
roughly 0.5 UI in this region. The corner frequency between the
declining slope and the flat region is the closed-loop bandwidth
of the delay-locked loop, which is roughly 5 MHz for OC-12,
OC-48, and GbE data rates, and 600 kHz for OC-3 data rates.
Rev. B | Page 13 of 24
JITTER PEAKING
IN ORDINARY PLL
ADN2819
Z(s)
X(s)
f
(kHz)
JITTER
GAIN
(dB)
o
n psh
d psh
c
0
Figure 16. Jitter Response vs. Conventional PLL
相關(guān)PDF資料
PDF描述
ADN2819ACP-CML-RL Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp
ADN2819ACPZ-CML-RL1 Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp
ADN2819ACPZ-CML1 Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp
ADN2830ACP32-REEL Circular Connector; No. of Contacts:4; Series:LJT06R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:21; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:21-75
ADN2830ACP32-REEL7 Circular Connector; No. of Contacts:4; Series:LJT06R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:21; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:21-75
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADN2819ACP-CML-RL 制造商:Analog Devices 功能描述:CDR 2488.32Mbps/2666.06Mbps SONET/SDH 48-Pin LFCSP EP T/R
ADN2819ACPZ-CML 功能描述:IC CLOCK/DATA RECOVERY 48LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無(wú)/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件
ADN2819ACPZ-CML1 制造商:AD 制造商全稱:Analog Devices 功能描述:Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp
ADN2819ACPZ-CML-RL 功能描述:IC CLOCK/DATA RECOVERY 48LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無(wú)/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件
ADN2819ACPZ-CML-RL1 制造商:AD 制造商全稱:Analog Devices 功能描述:Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp
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