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參數(shù)資料
| 型號： | ADN2818ACPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 21/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK/DATA RECOVERY 32-LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時(shí)鐘和數(shù)據(jù)恢復(fù)（CDR），多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | SONET/SDH |
| 輸入： | CML |
| 輸出： | CML |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.7GHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 788 (CN2011-ZH PDF) |
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ADN2817/ADN2818
Data Sheet
Rev. E | Page 28 of 40
ADDITIONAL FEATURES AVAILABLE VIA THE I2C
INTERFACE
Coarse Data Rate Readback
The data rate can be read back over the I2C interface to
approximately ±10% without needing an external reference
clock. A 9-bit register, COARSE_RD[8:0], can be read back
when LOL is deasserted. The eight MSBs of this register are the
contents of the Rate[7:0] register. The LSB of the COARSE_RD
register is Bit MISC[0].
Table 19 is a look-up table (LUT) that provides coarse data rate
readback values to within ±10%.
LOS Configuration
The LOS detector output, Pin 22 (LOS), can be configured as
either active high or active low. If CTRLC[2] is set to Logic 0
(default), the LOS pin is active high when a loss of signal
condition is detected. Writing a 1 to CTRLC[2] configures
the LOS pin to be active low when a loss of signal condition
is detected.
Initiate Frequency Acquisition
A frequency acquisition can be initiated by writing a 1 followed
by a 0 to the I2C Register Bit CTRLB[5]. This initiates a new
frequency acquisition while keeping the ADN2817/ADN2818
in the operating mode that was previously programmed in the
CTRLA, CTRLB, CTRLC, CTRLD, and CTRLE registers.
Rate Selectivity
The ADN2817/ADN2818 can operate in a limited range mode
in situations where the user wants to restrict the data rates to
which the device can lock. In this mode, the frequency acquisition
range of the device is limited to a specific range of data rates.
The acquisition range is determined by programming an upper
and lower 9-bit code into the HI_CODE[8:1], LO_CODE[8:1],
table (LUT) showing the correct register settings for each data
rate. Table 20 has three columns: code, high limit, and low limit.
The user programs the code value for the high limit data rate
into HI_CODE and the code value for the low limit data rate
into LO_CODE to set the appropriate range.
For example, if the user wants to limit the acquisition range of
the ADN2817/ADN2818 to lock between 1 Gbps and 1.25 Gbps,
the following steps must be taken:
1. Find the first code in Table 20 that corresponds to a data
rate below 1.0 Gbps in the low limit column, that is, Code 236
or 011101100b. Set LO_CODE[8:1] = 01110110b
(LO_CODE[0] is set in Register Bit CODE_LSB[0].)
2. Find the first code in Table 20 that corresponds to a data
rate above 1.25 Gbps in the high limit column, that is,
Code 258 or 100000010b. Set HI_CODE[8:1] = 10000001b
(HI_CODE[0] is set in Register Bit CODE_LSB[1].)
3. Set CODE_LSB = 00000000b given that the HI_CODE[0]
= 0 and LO_CODE[0] = 0.
4. Set SEL_MODE[3] = 1.
5. When there is a valid input to the device between 1.0 Gbps
and 1.25 Gbps, write a 1-to-0 transition into CTRLB[5] to
initiate a new frequency acquisition.
Double Data Rate Mode
Setting CTRLE = 0x02 puts the ADN2817/ADN2818 clock
output through divide-by-two circuitry allowing direct
interfacing to FPGAs that support data clocking on both
rising and falling edges.
PRBS Generator/Detector
The ADN2817/ADN2818 have an integrated PRBS generator/
detector for system testing purposes. The devices are configurable
as either a PRBS detector or a PRBS generator. The two functions
cannot be used at the same time.
The following steps configure the PRBS detector (PRBS 7 only):
1. Set CTRLE[2:0] = 0x5.
2. Set CTRLD[2:0] = 0x4 to enable the PRBS detector.
The PRBS error signal outputs on the DATAOUTP/DATAOUTN
pins. Every time the PRBS detector detects an error, the
DATAOUTP/DATAOUTN outputs pulse twice to a Logic 1,
that is, DATAOUTP = 1, DATAOUTN = 0.
The following steps configure the PRBS generator (PRBS 7 only):
1. Set CTRLE[2:0] = 0x5.
2. Set CTRLD[2:0] = 0x1 to enable the PRBS generator.
3. Write a 1-to-0 transition into CTRLD[3] to initiate a
PRBS 7 pattern.
Note that the PRBS generator is clocked by the VCO; therefore,
the user needs to feed in a clock at half the desired frequency.
For example, for an OC-48 PRBS pattern, input a 1.244 GHz
clock to PIN/NIN. This appears as a 2.488 Gbps NRZ data
pattern to the ADN2817/ADN2818. The recovered clock is
2.488 GHz, which clocks the PRBS generator to produce an
OC-48 PRBS pattern on the outputs.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADN2818ACPZ-RL | 制造商:AD 制造商全稱:Analog Devices 功能描述:Continuous Rate 10 Mbps to 2.7 Gbps Clock and Data Recovery ICs |
| ADN2818ACPZ-RL7 | 功能描述:IC CLOCK/DATA RECOVERY 32-LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| ADN2819 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp |
| ADN2819ACP-CML | 制造商:Analog Devices 功能描述:CDR 2488.32Mbps/2666.06Mbps SONET/SDH 48-Pin LFCSP EP Tray 制造商:Rochester Electronics LLC 功能描述:MULTI-RATE 2.7GBPS CDR/ PA LOW POWER I.C - Bulk |
| ADN2819ACP-CML-RL | 制造商:Analog Devices 功能描述:CDR 2488.32Mbps/2666.06Mbps SONET/SDH 48-Pin LFCSP EP T/R |
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