參數(shù)資料
型號： ADN2818ACPZ-RL7
廠商： Analog Devices Inc
文件頁數(shù)： 26/40頁
文件大?。?/td> 0K
描述： IC CLOCK/DATA RECOVERY 32-LFCSP
標(biāo)準(zhǔn)包裝： 1,500
類型： 時(shí)鐘和數(shù)據(jù)恢復(fù)（CDR），多路復(fù)用器
PLL： 是
主要目的： SONET/SDH
輸入： CML
輸出： CML
電路數(shù)： 1
比率 - 輸入:輸出： 1:2
差分 - 輸入:輸出： 是/是
頻率 - 最大： 2.7GHz
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-VQ（5x5）
包裝： 帶卷 (TR)
ADN2817/ADN2818
Data Sheet
Rev. E | Page 32 of 40
NOTES
1. DURING THE DATA PATTERNS WITH HIGH TRANSITION DENSITY, DIFFERENTIAL DC VOLTAGE AT V1 AND V2 IS ZERO.
2. WHEN THE OUTPUT OF THE TIA GOES TO CID, V1 AND V1b ARE DRIVEN TO DIFFERENT DC LEVELS. V2 AND V2b DISCHARGE TO THE VREF
LEVEL WHICH EFFECTIVELY INTRODUCES A DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS.
3. WHEN THE BURST OF DATA STARTS AGAIN, THE DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS IS APPLIED TO THE
INPUT LEVELS CAUSING A DC SHIFT IN THE DIFFERENTIAL INPUT. THIS SHIFT IS LARGE ENOUGH SUCH THAT ONE OF THE STATES, EITHER
HIGH OR LOW DEPENDING ON THE LEVELS OF V1 AND V1b WHEN THE TIA WENT TO CID, IS CANCELLED OUT. THE QUANTIZER DOES NOT
RECOGNIZE THIS AS A VALID STATE.
4. THE DC OFFSET SLOWLY DISCHARGES UNTIL THE DIFFERENTIAL INPUT VOLTAGE EXCEEDS THE SENSITIVITY OF THE ADN2817. THE
QUANTIZER RECOGNIZES BOTH HIGH AND LOW STATES AT THIS POINT.
V1
V1b
V2
V2b
VDIFF
VDIFF = V2 – V2b
VTH = ADN2817 QUANTIZER THRESHOLD
2
34
1
VREF
VTH
CDR
LIMAMP
VREF
50
PIN
NIN
ADN2817
COUT
DATAOUTP
DATAOUTN
CIN
V2
V2b
V1
V1b
TIA
VCC
06
00
1-
02
8
Figure 39. Example of Baseline Wander
DC-COUPLED APPLICATION
The inputs to the ADN2817/ADN2818 can also be dc-coupled.
This can be necessary in burst mode applications with long periods
of CIDs and where baseline wander cannot be tolerated. If the
inputs to the ADN2817/ADN2818 are dc-coupled, care must be
taken not to violate the input range and common-mode level
requirements of the ADN2817/ADN2818 (see Figure 40 through
Figure 42). If dc coupling is required, and the output levels of
the TIA do not adhere to the levels shown in Figure 41, level
shifting and/or attenuation must occur between the TIA
outputs and the ADN2817/ADN2818 inputs.
50
2.5V
ADN2817/ADN2818
VCC
TIA
PIN
NIN
3k
VREF
0.1F
TIA
06
00
1-
0
29
Figure 40. DC-Coupled Application
PIN
IN
P
U
T
(
V
)
V p-p = PIN – NIN = 2 × VSE = 10mV AT SENSITIVITY
VSE = 5mV MIN
VCM = 2.3V MIN
(DC-COUPLED)
NIN
0
600
1-
03
0
Figure 41. Minimum Allowed DC-Coupled Input Levels
PIN
IN
P
U
T
(
V
)
V p-p = PIN – NIN = 2 × VSE = 2.0V MAX
VSE = 1.0V MAX
VCM = 2.3V
(DC-COUPLED)
NIN
0
600
1-
03
1
Figure 42. Maximum Allowed DC-Coupled Input Levels
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