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參數(shù)資料
| 型號： | ADN2818ACPZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 22/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK/DATA RECOVERY 32-LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 類型： | 時鐘和數(shù)據(jù)恢復(fù)（CDR），多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | SONET/SDH |
| 輸入： | CML |
| 輸出： | CML |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.7GHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 帶卷 (TR) |
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Data Sheet
ADN2817/ADN2818
Rev. E | Page 29 of 40
CLK Holdover Mode
This mode of operation is available in LTD mode. In CLK
holdover mode, the output clock frequency remains within
±5% if the input data is removed or changed. To operate in
this mode, the user writes to the I2C to put the part into CLK
holdover mode by setting SEL_MODE[1] = 1. The user must
then initiate a frequency acquisition by writing a 1-to-0 transi-
tion into CTRLB[5], at which time the device locks onto the
input data rate. At this point, the output frequency remains
within ±5% of the initial acquired value regardless of whether
the input data is removed or the data rate changes.
It is important to note that all frequency acquisitions in this
mode must be initiated by writing a 1-to-0 transition into
CTRLB[5]. In this mode, the device does not automatically
initiate a new frequency acquisition when the input is momen-
tarily interrupted or if the input data rate changes.
CDR Bypass Mode
The CDR on the ADN2817/ADN2818 can be bypassed by setting
Bit CTRLD[7] = 1. In this mode, the ADN2817/ADN2818 feed
the input directly through the input amplifiers to the output
buffer, completely bypassing the CDR.
Disable Output Buffers
The ADN2817/ADN2818 provide the option of disabling the
output buffers for power savings. The clock output buffers
can be disabled by setting Bit CTRLD[5] = 1. This reduces
the total power consumption of the device by ~100 mW. For
an additional 100 mW power savings, such as in low power
standby mode, the data output buffers can also be disabled by
setting Bit CTRLD[6] = 1.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADN2819 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp |
| ADN2819ACP-CML | 制造商:Analog Devices 功能描述:CDR 2488.32Mbps/2666.06Mbps SONET/SDH 48-Pin LFCSP EP Tray 制造商:Rochester Electronics LLC 功能描述:MULTI-RATE 2.7GBPS CDR/ PA LOW POWER I.C - Bulk |
| ADN2819ACP-CML-RL | 制造商:Analog Devices 功能描述:CDR 2488.32Mbps/2666.06Mbps SONET/SDH 48-Pin LFCSP EP T/R |
| ADN2819ACPZ-CML | 功能描述:IC CLOCK/DATA RECOVERY 48LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| ADN2819ACPZ-CML1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp |
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