參數(shù)資料
型號： ADN2812ACPZ
廠商： Analog Devices Inc
文件頁數(shù)： 15/28頁
文件大?。?/td> 0K
描述： IC CLOCK/DATA RECOVERY 32LFCSP
標準包裝： 1
類型： 時鐘和數(shù)據(jù)恢復(fù)（CDR），多路復(fù)用器
PLL： 是
主要目的： SONET/SDH
輸入： CML
輸出： CML
電路數(shù)： 1
比率 - 輸入:輸出： 1:2
差分 - 輸入:輸出： 是/是
頻率 - 最大： 2.7GHz
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-VQ（5x5）
包裝： 托盤
ADN2812
Data Sheet
Rev. E | Page 22 of 28
Transmission Lines
Use of 50 transmission lines is required for all high frequency
input and output signals to minimize reflections: PIN, NIN,
CLKOUTP, CLKOUTN, DATAOUTP, DATAOUTN (also
REFCLKP, REFCLKN, if a high frequency reference clock is
used, such as 155 MHz). It is also necessary for the PIN/NIN
input traces to be matched in length and the CLKOUTP/
CLKOUTN and DATAOUTP/DATAOUTN output traces to
be matched in length to avoid skew between the differential
traces. All high speed CML outputs, CLKOUTP/CLKOUTN
and DATAOUTP/DATAOUTN, also require 100 back
termination chip resistors connected between the output pin
and VCC. These resistors should be placed as close as possible
to the output pins. These 100 resistors are in parallel with
on-chip 100 termination resistors to create a 50 back
termination (see Figure 25).
The high speed inputs, PIN and NIN, are internally terminated
with 50 to an internal reference voltage (see Figure 26). A 0.1 F
is recommended between VREF (Pin 3) and GND to provide an
ac ground for the inputs.
As with any high speed mixed-signal design, take care to keep
all high speed digital traces away from sensitive analog nodes.
04228-
025
ADN2812
0.1F
100Ω 100Ω
VCC
100Ω 100Ω
VCC
50Ω
VTERM
50Ω
Figure 25. Typical ADN2812 Applications Circuit
04228-
026
CIN
50Ω
0.1F
50Ω
3kΩ
NIN
PIN
ADN2812
2.5V
VREF
50Ω
TIA
VCC
Figure 26. ADN2812 AC-Coupled Input Configuration
Soldering Guidelines for Chip Scale Package
The leads on the 32-lead LFCSP are rectangular. The printed
circuit board pad for these should be 0.1 mm longer than the
package lead length and 0.05 mm wider than the package lead
width. The lead should be centered on the pad. This ensures
that the solder joint size is maximized. The bottom of the chip
scale package has a central exposed pad. The pad on the printed
circuit board should be at least as large as this exposed pad. The
user must connect the exposed pad to VEE using plugged vias
so that solder does not leak through the vias during reflow. This
ensures a solid connection from the exposed pad to VEE.
Choosing AC Coupling Capacitors
AC coupling capacitors at the inputs (PIN, NIN) and outputs
(DATAOUTP, DATAOUTN) of the ADN2812 must be chosen
such that the device works properly over the full range of data
rates used in the application. When choosing the capacitors, the
time constant formed with the two 50 resistors in the signal
path must be considered. When a large number of consecutive
identical digits (CIDs) are applied, the capacitor voltage can
droop due to baseline wander (see Figure 27), causing pattern-
dependent jitter (PDJ).
The user must determine how much droop is tolerable and
choose an ac coupling capacitor based on that amount of
droop. The amount of PDJ can then be approximated based
on the capacitor selection. The actual capacitor value selection
may require some trade-offs between droop and PDJ.
For example, assuming that 2% droop can be tolerated, then the
maximum differential droop is 4%. Normalizing to Vpp
Droop = V = 0.04 V = 0.5 Vpp(1 e–t/τ); therefore, τ = 12t
where:
τ is the RC time constant (C is the ac coupling capacitor,
R = 100 seen by C).
t is the total discharge time, which is equal to nΤ.
n is the number of CIDs.
T is the bit period.
The capacitor value can then be calculated by combining the
equations for τ and t
R
nT
C
/
12
=
Once the capacitor value is selected, the PDJ can be
approximated as
(
)
(
) 6.
0
/
1
5
.
0 r
nT/RC
pspp
e
t
PDJ
/
=
where:
PDJpspp is the amount of pattern-dependent jitter allowed;
< 0.01 UI p-p typical.
tr is the rise time, which is equal to 0.22/BW, where BW is ~ 0.7
(bit rate). This expression for tr is accurate only for the inputs.
The output rise time for the ADN2812 is ~100 ps regardless of
data rate.
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