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參數(shù)資料
| 型號(hào)： | ADN2812ACP-RL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp |
| 中文描述： | CLOCK RECOVERY CIRCUIT, QCC32 |
| 封裝： | 5 X 5 MM, MO-220VHHD-2, LFCSP-32 |
| 文件頁(yè)數(shù)： | 3/28頁(yè) |
| 文件大?。?/td> | 478K |
| 代理商： | ADN2812ACP-RL |
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ADN2812
SPECIFICATIONS
T
A
= T
MIN
to T
MAX
, VCC = V
MIN
to V
MAX
, VEE = 0 V, C
F
= 0.47 μF, SLICEP = SLICEN = VEE, Input Data Pattern: PRBS 2
23
1,
unless otherwise noted.
Table 1.
Parameter
Conditions
QUANTIZER—DC CHARACTERISTICS
Input Voltage Range
@ PIN or NIN, dc-coupled
Peak-to-Peak Differential Input
PIN – NIN
DC-coupled (see Figure 28, Figure 29,
and Figure 30)
Differential Input Sensitivity
2
23
1 PRBS, ac-coupled,
1
BER = 1 x 10
–10
Input Overdrive
(see Figure 12)
Input Offset
Input RMS Noise
BER = 1 x 10
–10
QUANTIZER—AC CHARACTERISTICS
Data Rate
S11
@ 2.5 GHz
Input Resistance
Differential
Input Capacitance
QUANTIZER—SLICE ADJUSTMENT
Gain
SLICEP – SLICEN = ±0.5 V
Differential Control Voltage Input
SLICEP – SLICEN
Control Voltage Range
DC level @ SLICEP or SLICEN
Slice Threshold Offset
LOSS OF SIGNAL DETECT (LOS)
Loss of Signal Detect Range (see Figure 5)
R
Thresh
= 0
R
Thresh
= 100 k
Hysteresis (Electrical)
OC-48
R
Thresh
= 0
R
Thresh
= 100 k
OC-1
R
Thresh
= 0
R
Thresh
= 10 k
LOS Assert Time
DC-coupled
2
LOS De-Assert Time
DC-coupled
2
LOSS OF LOCK DETECT (LOL)
VCO Frequency Error for LOL Assert
With respect to nominal
VCO Frequency Error for LOL De-Assert
With respect to nominal
LOL Response Time
12.3 Mb/s
OC-12
OC-48
ACQUISITION TIME
Lock to Data Mode
OC-48
OC-12
OC-3
OC-1
12.3 Mb/s
Optional Lock to REFCLK Mode
Rev. 0 | Page 3 of 28
Min
1.8
Typ
Max
2.8
2.0
2.8
Unit
V
V
Input Common Mode Level
2.3
2.5
V
10
5
12.3
0.08
–0.95
VEE
12
2.0
5.6
3.7
5.6
2.0
6
3
500
290
15
100
0.65
0.1
1
15
3.0
6
6
6
4
500
400
1000
250
4
1.0
1.0
1.3
2.0
3.4
9.8
40.0
10.0
2700
0.12
+0.95
0.95
17
4.0
7.2
8.4
7.2
6.7
mV p-p
mV p-p
μV
μV rms
Mb/s
dB
pF
V/V
V
V
mV
mV
mV
dB
dB
dB
dB
ns
ns
ppm
ppm
ms
μs
μs
ms
ms
ms
ms
ms
ms
1
PIN and NIN should be differentially driven and ac-coupled for optimum sensitivity.
2
When ac-coupled, the LOS assert and de-assert time is dominated by the RC time constant of the ac coupling capacitor and the 50 input termination of the
ADN2812 input stage.
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