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參數(shù)資料
| 型號： | ADN2812ACP-RL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp |
| 中文描述： | CLOCK RECOVERY CIRCUIT, QCC32 |
| 封裝： | 5 X 5 MM, MO-220VHHD-2, LFCSP-32 |
| 文件頁數(shù)： | 20/28頁 |
| 文件大?。?/td> | 478K |
| 代理商： | ADN2812ACP-RL |
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ADN2812
Use the following equation to determine the data rate:
(
22
DATARATE
FREQ
f
Rev. 0 | Page 20 of 28
[
]
)
)
_
14
(
2
/
0
..
RATE
SEL
REFCLK
f
+
×
=
where:
FREQ[22:0] is the reading from FREQ2[6:0] (MSByte),
FREQ1[7:0], and FREQ0[7:0] (LSByte).
Table 12.
D22
D21...D17
D16
D15
FREQ2[6:0]
D14...D9
FREQ1[7:0]
D8
D7
D6...D1
FREQ0[7:0]
D0
f
DATARATE
is the data rate (Mb/s).
f
REFCLK
is the REFCLK frequency (MHz).
SEL_RATE
is the setting from CTRLA[7:6].
For example, if the reference clock frequency is 32 MHz,
SEL_RATE = 1, since the CTRLA[7:6] setting would be [01],
because the reference frequency would fall into the 25 MHz to
50 MHz range. Assume for this example that the input data rate
is 2.488 Gb/s (OC-48). After following Steps 1 through 4, the
value that is read back on FREQ[22:0] = 0x26E010, which is
equal to 2.5477 × 10
6
. Plugging this value into the equation
yields
(
2
/
6
e
32
6
e
5477
.
×
)
(
)
Gb/s
488
.
)
+
14
(
=
If subsequent frequency measurements are required, CTRLA[1]
should remain set to 1. It does not need to be reset. The
measurement process is reset by writing a 1 followed by a 0 to
CTRLB[3]. This initiates a new data rate measurement. Follow
Steps 2 through 4 to read back the new data rate.
Note: A data rate readback is valid only if LOL is low. If LOL is
high, the data rate readback is invalid.
Additional Features Available via the I
2
C Interface
Coarse Data Rate Readback
The data rate can be read back over the I
2
C interface to
approximately +10% without the need of an external reference
clock. A 9-bit register, COARSE_RD[8:0], can be read back
when LOL is de-asserted. The 8 MSBs of this register are the
contents of the RATE[7:0] register. The LSB of the
COARSE_RD register is Bit MISC[0].
Table 13 provides coarse data rate readback to within ±10%.
LOS Configuration
The LOS detector output, LOS Pin 22, can be configured to be
either active high or active low. If CTRLC[2] is set to Logic 0
(default), the LOS pin is active high when a loss of signal
condition is detected. Writing a 1 to CTRLC[2] configures the
LOS pin to be active low when a loss of signal condition is
detected.
System Reset
A frequency acquisition can be initiated by writing a 1 followed
by a 0 to the I
2
C Register Bit CTRLB[5]. This initiates a new
frequency acquisition while keeping the ADN2812 in the
operating mode that it was previously programmed to in
registers CTRL[A], CTRL[B], and CTRL[C].
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