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參數(shù)資料
| 型號(hào)： | ADN2812ACP-RL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp |
| 中文描述： | CLOCK RECOVERY CIRCUIT, QCC32 |
| 封裝： | 5 X 5 MM, MO-220VHHD-2, LFCSP-32 |
| 文件頁數(shù)： | 19/28頁 |
| 文件大?。?/td> | 478K |
| 代理商： | ADN2812ACP-RL7 |
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ADN2812
The two uses of the reference clock are mutually exclusive. The
reference clock can be used either as an acquisition aid for the
ADN2812 to lock onto data, or to measure the frequency of the
incoming data to within 0.01%. (There is the capability to
measure the data rate to approximately ±10
%
without the use of
a reference clock.) The modes are mutually exclusive, because,
in the first use, the user knows exactly what the data rate is and
wants to force the part to lock onto only that data rate; in the
second use, the user does not know what the data rate is and
wants to measure it.
Rev. 0 | Page 19 of 28
Lock to reference mode is enabled by writing a 1 to I
2
C Register
Bit CTRLA[0]. Fine data rate readback mode is enabled by
writing a 1 to I
2
C Register Bit CTRLA[1]. Writing a 1 to both of
these bits at the same time causes an indeterminate state and is
not supported.
Using the Reference Clock to Lock onto Data
In this mode, the ADN2812 locks onto a frequency derived
from the reference clock according to the following equation:
Data Rate
/2
CTRLA[5:2]
=
REFCLK
/2
CTRLA[7:6]
The user must know exactly what the data rate is, and provide a
reference clock that is a function of this rate. The ADN2812 can
still be used as a continuous rate device in this configuration,
provided that the user has the ability to provide a reference
clock that has a variable frequency (see Application Note
AN-632).
The reference clock can be anywhere between 12.3 MHz and
200 MHz. By default, the ADN2812 expects a reference clock of
between 12.3 MHz and 25 MHz. If it is between 25 MHz and
50 MHz, 50 MHz and 100 MHz, or 100 MHz and 200 MHz, the
user needs to configure the ADN2812 to use the correct
reference frequency range by setting two bits of the CTRLA
register, CTRLA[7:6].
Table 11. CTRLA Settings
CTRLA[7:6]
Range (MHz)
00
12.3 to 25
01
25 to 50
10
50 to 100
11
100 to 200
CTRLA[5:2]
0000
0001
n
1000
Ratio
1
2
2
n
256
The user can specify a fixed integer multiple of the reference
clock to lock onto using CTRLA[5:2], where CTRLA should be
set to the data rate/DIV_F
REF
, where DIV_F
REF
represents the
divided-down reference referred to the 12.3 MHz to 25 MHz
band. For example, if the reference clock frequency was
38.88 MHz and the input data rate was 622.08 Mb/s, then
CTRLA[7:6] would be set to [01] to give a divided-down
reference clock of 19.44 MHz. CTRLA[5:2] would be set to
[0101], that is, 5, because
622.08 Mb/s/19.44 MHz = 2
5
In this mode, if the ADN2812 loses lock for any reason, it
relocks onto the reference clock and continues to output a stable
clock.
While the ADN2812 is operating in lock to reference mode, if
the user ever changes the reference frequency, the F
REF
range
(CTRLA[7:6]), or the F
REF
ratio (CTRLA[5:2]), this must be
followed by writing a 0 to 1 transition into the CTRLA[0] bit to
initiate a new lock to reference command.
Using the Reference Clock to Measure Data Frequency
The user can also provide a reference clock to measure the
recovered data frequency. In this case, the user provides a
reference clock, and the ADN2812 compares the frequency of
the incoming data to the incoming reference clock and returns a
ratio of the two frequencies to 0.01% (100 ppm). The accuracy
error of the reference clock is added to the accuracy of the
ADN2812 data rate measurement. For example, if a 100-ppm
accuracy reference clock is used, the total accuracy of the
measurement is within 200 ppm.
The reference clock can range from 12.3 MHz and 200 MHz.
The ADN2812 expects a reference clock between 12.3 MHz and
25 MHz by default. If it is between 25 MHz and 50 MHz,
50 MHz and 100 MHz, or 100 MHz and 200 MHz, the user
needs to configure the ADN2812 to use the correct reference
frequency range by setting two bits of the CTRLA register,
CTRLA[7:6]. Using the reference clock to determine the
frequency of the incoming data does not affect the manner in
which the part locks onto data. In this mode, the reference clock
is used only to determine the frequency of the data. For this
reason, the user does not need to know the data rate to use the
reference clock in this manner.
Prior to reading back the data rate using the reference clock, the
CTRLA[7:6] bits must be set to the appropriate frequency range
with respect to the reference clock being used. A fine data rate
readback is then executed as follows:
Step 1: Write a 1 to CTRLA[1]. This enables the fine data rate
measurement capability of the ADN2812. This bit is level
sensitive and does not need to be reset to perform subsequent
frequency measurements.
Step 2: Reset MISC[2] by writing a 1 followed by a 0 to
CTRLB[3]. This initiates a new data rate measurement.
Step 3: Read back MISC[2]. If it is 0, then the measurement is
not complete. If it is 1, then the measurement is complete and
the data rate can be read back on FREQ[22:0]. The time for a
data rate measurement is typically 80 ms.
Step 4: Read back the data rate from registers FREQ2[6:0],
FREQ1[7:0], and FREQ0[7:0].
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