參數(shù)資料
型號(hào)： ADN2812
廠商： Analog Devices, Inc.
元件分類： 運(yùn)動(dòng)控制電子
英文描述： Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp
中文描述： 連續(xù)速率12.3 Mb / s的2.7 Gb / s的集成時(shí)鐘和數(shù)據(jù)恢復(fù)芯片限幅放大器
文件頁數(shù)： 3/28頁
文件大小： 478K
代理商： ADN2812
ADN2812
SPECIFICATIONS
T
A
= T
MIN
to T
MAX
, VCC = V
MIN
to V
MAX
, VEE = 0 V, C
F
= 0.47 μF, SLICEP = SLICEN = VEE, Input Data Pattern: PRBS 2
23
1,
unless otherwise noted.
Table 1.
Parameter
Conditions
QUANTIZER—DC CHARACTERISTICS
Input Voltage Range
@ PIN or NIN, dc-coupled
Peak-to-Peak Differential Input
PIN – NIN
DC-coupled (see Figure 28, Figure 29,
and Figure 30)
Differential Input Sensitivity
2
23
1 PRBS, ac-coupled,
1
BER = 1 x 10
–10
Input Overdrive
(see Figure 12)
Input Offset
Input RMS Noise
BER = 1 x 10
–10
QUANTIZER—AC CHARACTERISTICS
Data Rate
S11
@ 2.5 GHz
Input Resistance
Differential
Input Capacitance
QUANTIZER—SLICE ADJUSTMENT
Gain
SLICEP – SLICEN = ±0.5 V
Differential Control Voltage Input
SLICEP – SLICEN
Control Voltage Range
DC level @ SLICEP or SLICEN
Slice Threshold Offset
LOSS OF SIGNAL DETECT (LOS)
Loss of Signal Detect Range (see Figure 5)
R
Thresh
= 0
R
Thresh
= 100 k
Hysteresis (Electrical)
OC-48
R
Thresh
= 0
R
Thresh
= 100 k
OC-1
R
Thresh
= 0
R
Thresh
= 10 k
LOS Assert Time
DC-coupled
2
LOS De-Assert Time
DC-coupled
2
LOSS OF LOCK DETECT (LOL)
VCO Frequency Error for LOL Assert
With respect to nominal
VCO Frequency Error for LOL De-Assert
With respect to nominal
LOL Response Time
12.3 Mb/s
OC-12
OC-48
ACQUISITION TIME
Lock to Data Mode
OC-48
OC-12
OC-3
OC-1
12.3 Mb/s
Optional Lock to REFCLK Mode
Rev. 0 | Page 3 of 28
Min
1.8
Typ
Max
2.8
2.0
2.8
Unit
V
V
Input Common Mode Level
2.3
2.5
V
10
5
12.3
0.08
–0.95
VEE
12
2.0
5.6
3.7
5.6
2.0
6
3
500
290
15
100
0.65
0.1
1
15
3.0
6
6
6
4
500
400
1000
250
4
1.0
1.0
1.3
2.0
3.4
9.8
40.0
10.0
2700
0.12
+0.95
0.95
17
4.0
7.2
8.4
7.2
6.7
mV p-p
mV p-p
μV
μV rms
Mb/s
dB
pF
V/V
V
V
mV
mV
mV
dB
dB
dB
dB
ns
ns
ppm
ppm
ms
μs
μs
ms
ms
ms
ms
ms
ms
1
PIN and NIN should be differentially driven and ac-coupled for optimum sensitivity.
2
When ac-coupled, the LOS assert and de-assert time is dominated by the RC time constant of the ac coupling capacitor and the 50 input termination of the
ADN2812 input stage.
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ADN2812ACPZ 功能描述:IC CLOCK/DATA RECOVERY 32LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:時(shí)鐘/頻率發(fā)生器，多路復(fù)用器 PLL:是 主要目的:存儲(chǔ)器，RDRAM 輸入:晶體 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:Digi-Reel® 其它名稱:296-6719-6
ADN2812ACPZ-RL 功能描述:IC CLOCK/DATA RECOVERY 32LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件
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