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參數(shù)資料
| 型號： | ADN2812 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 運動控制電子 |
| 英文描述： | Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp |
| 中文描述： | 連續(xù)速率12.3 Mb / s的2.7 Gb / s的集成時鐘和數(shù)據(jù)恢復芯片限幅放大器 |
| 文件頁數(shù)： | 14/28頁 |
| 文件大?。?/td> | 478K |
| 代理商： | ADN2812 |
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ADN2812
THEORY OF OPERATION
The ADN2812 is a delay- and phase-locked loop circuit for
clock recovery and data retiming from an NRZ encoded data
stream. The phase of the input data signal is tracked by two
separate feedback loops, which share a common control voltage.
A high speed delay-locked loop path uses a voltage controlled
phase shifter to track the high frequency components of input
jitter. A separate phase control loop, comprised of the VCO,
tracks the low frequency components of input jitter. The initial
frequency of the VCO is set by yet a third loop, which compares
the VCO frequency with the input data frequency and sets the
coarse tuning voltage. The jitter tracking phase-locked loop
controls the VCO by the fine-tuning control.
Rev. 0 | Page 14 of 28
The delay- and phase-loops together track the phase of the
input data signal. For example, when the clock lags input data,
the phase detector drives the VCO to higher frequency, and also
increases the delay through the phase shifter; both these actions
serve to reduce the phase error between the clock and data. The
faster clock picks up phase, while the delayed data loses phase.
Because the loop filter is an integrator, the static phase error is
driven to zero.
Another view of the circuit is that the phase shifter implements
the zero required for frequency compensation of a second-
order phase-locked loop, and this zero is placed in the feedback
path and, thus, does not appear in the closed-loop transfer
function. Jitter peaking in a conventional second-order phase-
locked loop is caused by the presence of this zero in the closed-
loop transfer function. Because this circuit has no zero in the
closed-loop transfer, jitter peaking is minimized.
The delay- and phase-loops together simultaneously provide
wide-band jitter accommodation and narrow-band jitter
filtering. The linearized block diagram in Figure 17 shows that
the jitter transfer function, Z(s)/X(s), is a second-order low-pass
providing excellent filtering. Note that the jitter transfer has no
zero, unlike an ordinary second-order phase-locked loop. This
means that the main PLL loop has virtually zero jitter peaking
(see Figure 18). This makes this circuit ideal for signal regen-
erator applications, where jitter peaking in a cascade of
regenerators can contribute to hazardous jitter accumulation.
The error transfer, e(s)/X(s), has the same high-pass form as an
ordinary phase-locked loop. This transfer function is free to be
optimized to give excellent wide-band jitter accommodation,
because the jitter transfer function, Z(s)/X(s), provides the
narrow-band jitter filtering.
0
X(s)
Z(s)
RECOVERED
CLOCK
e(s)
INPUT
DATA
d/sc
psh
o/s
1/n
d = PHASE DETECTOR GAIN
o = VCO GAIN
c = LOOP INTEGRATOR
psh = PHASE SHIFTER GAIN
n = DIVIDE RATIO
=
1
cn
do
s
2
+
n psh
o
s
+ 1
Z(s)
X(s)
JITTER TRANSFER FUNCTION
=
s
2
s
2
d psh
c
s
+
+cn
e(s)
X(s)
TRACKING ERROR TRANSFER FUNCTION
Figure 17. ADN2812 PLL/DLL Architecture
ADN2812
Z(s)
X(s)
0
FREQUENCY (kHz)
JITTER PEAKING
IN ORDINARY PLL
J
o
n psh
d psh
c
Figure 18. ADN2812 Jitter Response vs. Conventional PLL
The delay- and phase-loops contribute to overall jitter accom-
modation. At low frequencies of input jitter on the data signal,
the integrator in the loop filter provides high gain to track large
jitter amplitudes with small phase error. In this case, the VCO is
frequency modulated and jitter is tracked as in an ordinary
phase-locked loop. The amount of low frequency jitter that can
be tracked is a function of the VCO tuning range. A wider
tuning range gives larger accommodation of low frequency
jitter. The internal loop control voltage remains small for small
phase errors, so the phase shifter remains close to the center of
its range and thus contributes little to the low frequency jitter
accommodation.
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PDF描述 |
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| ADN2812ACP | Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp |
| ADN2812ACP-RL | Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp |
| ADN2812ACP-RL7 | Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADN2812ACP | 制造商:Analog Devices 功能描述:IC CLOCK/DATA RECOVERY |
| ADN2812ACP-RL | 制造商:Analog Devices 功能描述:Clock and Data Recovery 32-Pin LFCSP EP T/R |
| ADN2812ACP-RL7 | 制造商:Analog Devices 功能描述:Clock and Data Recovery 32-Pin LFCSP EP T/R |
| ADN2812ACPZ | 功能描述:IC CLOCK/DATA RECOVERY 32LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1 系列:- 類型:時鐘/頻率發(fā)生器，多路復用器 PLL:是 主要目的:存儲器，RDRAM 輸入:晶體 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:Digi-Reel® 其它名稱:296-6719-6 |
| ADN2812ACPZ-RL | 功能描述:IC CLOCK/DATA RECOVERY 32LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務器 輸入:時鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應商設備封裝:64-TSSOP 包裝:管件 |
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