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參數(shù)資料
| 型號： | ADMCF340BST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DashDSPTM 64-Lead Flash Mixed-Signal DSP with Enhanced Analog Front End |
| 中文描述： | 0-BIT, 10 MHz, OTHER DSP, PQFP64 |
| 封裝： | PLASTIC, LQFP-64 |
| 文件頁數(shù)： | 14/40頁 |
| 文件大小： | 415K |
| 代理商： | ADMCF340BST |
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REV. 0
ADMCF340
–14–
For example, for a 20 MHz CLKOUT and a desired PWM
switching frequency of 10 kHz (T
S
= 100
μ
s), the correct value
to load into the
PWMTM
Register is:
PWMTM
x E
0 3 8
=
=
=
20 10
2 10 10
1000
6
3
The largest value that can be written to the 16-bit PWMTM
Register is 0xFFFF = 65,535, which corresponds to a minimum
PWM switching frequency of:
f
Hz
PWM
,min
,
=
×
65 535
×
=
20
10
2
153
6
for a CLKOUT frequency of 20 MHz.
PWM Switching Dead Time: PWMDT Register
The second important PWM block parameter that must be
initialized is the switching dead time. This is a short delay time
introduced between turning off one PWM signal (e.g., AH) and
turning on its complementary signal (e.g., AL). This short time
delay is introduced to permit the power switch being turned off to
completely recover its blocking capability before the comple-
mentary switch is turned on. This time delay prevents a potentially
destructive short circuit condition from developing across the dc
link capacitor of a typical voltage source inverter.
Dead time is controlled by the PWMDT Register. The dead
time is inserted into the three pairs of PWM output signals. The
dead time,
T
D
, is related to the value in the PWMDT Register by:
T
PWMDT
T
PWMDT
f
CLKOUT
D
CK
=
×
×
=
×
2
2
Therefore, a
PWMDT
value of 0x00A (= 10) introduces a 1
μ
s
delay between the turn-off of any PWM signal (e.g., AH) and
the turn-on of its complementary signal (e.g., AL). The amount
of the dead time can therefore be programmed in increments of
2 T
CK
(or 100 ns for a 20 MHz CLKOUT). The PWMDT Register
is a 10-bit register. For a CLKOUT rate of 20 MHz its maximum
value of 0x3FF (= 1023) corresponds to a maximum programmed
dead time of:
T
T
50
s
D
CK
max
=
×
×
×
×
=
=
×
1023
1023
102
2
2
10
9
sec
μ
The dead time can be programmed to zero by writing 0 to the
PWMDT Register.
PWM Operating Mode: MODECTRL and SYSSTAT Registers
The PWM controller of the ADMCF340 can operate in two
distinct modes: single update mode and double update mode.
The operating mode of the PWM controller is determined by
the state of Bit 6 of the MODECTRL Register. If this bit is
cleared, the PWM operates in the single update mode. Setting
Bit 6 places the PWM in the double update mode. By default,
following either a peripheral reset or power-on, Bit 6 of the
MODECTRL Register is cleared. This means that the default
operating mode is single update mode.
In single update mode, a single PWMSYNC pulse is produced
in each PWM period. The rising edge of this signal marks
the start of a new PWM cycle and is used to latch new values
from the PWM configuration registers (PWMTM, PWMDT,
PWMPD, and PWMSYNCWT) and the PWM duty cycle registers
(PWMCHA, PWMCHB, and PWMCHC) into the three-phase
timing unit. The PWMSEG Register is also latched into the
output control unit on the rising edge of the PWMSYNC pulse.
In effect, this means that the parameters of the PWM signals can
be updated only once per PWM period at the start of each cycle.
Thus, the generated PWM patterns are symmetrical about the
midpoint of the switching period.
In double update mode, there is an additional PWMSYNC
pulse produced at the midpoint of each PWM period. The rising
edge of this new PWMSYNC pulse is again used to latch new
values of the PWM configuration registers, duty cycle registers,
and the PWMSEG Register. As a result, it is possible to alter
both the characteristics (switching frequency, dead time, mini-
mum pulsewidth, and PWMSYNC pulsewidth) and the output
duty cycles at the midpoint of each PWM cycle. Consequently,
it is possible to produce PWM switching patterns that are no
longer symmetrical about the midpoint of the period (asym-
metrical PWM patterns).
In the double update mode, operation in the first half or the
second half of the PWM cycle is indicated by Bit 3 of the
SYSSTAT Register. In double update mode, this bit is cleared
during operation in the first half of each PWM period (between
the rising edge of the original PWMSYNC pulse and the rising
edge of the new PWMSYNC pulse, which is introduced in
double update mode). Bit 3 of the SYSSTAT Register is set
during the second half of each PWM period. If required, a user
may determine the status of this bit during a PWMSYNC
interrupt service routine.
The advantages of the double update mode are that lower
harmonic voltages can be produced by the PWM process and
wider control bandwidths are possible. However, for a given PWM
switching frequency, the PWMSYNC pulses occur at twice the
rate in the double update mode. Because new duty cycle values
must be computed in each PWMSYNC interrupt service routine,
there is a larger computational burden on the DSP in the
double update mode.
Width of the PWMSYNC Pulse: PWMSYNCWT Register
The PWM controller of the ADMCF340 produces an internal
PWM synchronization pulse at a rate equal to the PWM switching
frequency in single update mode and at twice the PWM frequency
in the double update mode. This PWMSYNC synchronizes the
operation of the PWM unit with the A/D converter system.
The width of this PWMSYNC pulse is programmable by the
PWMSYNCWT
Register. The width of the PWMSYNC pulse,
T
PWMSYNC
, is given by:
(
T
T
PWMSYNCWT
PWMSYNC
CK
=
×
+
)
1
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