參數(shù)資料
型號: ADMCF340
廠商: Analog Devices, Inc.
英文描述: DashDSPTM 64-Lead Flash Mixed-Signal DSP with Enhanced Analog Front End
中文描述: DashDSPTM 64無鉛閃存混合信號增強(qiáng)的DSP與模擬前端
文件頁數(shù): 19/40頁
文件大?。?/td> 415K
代理商: ADMCF340
REV. 0
ADMCF340
–19–
SWITCHED RELUCTANCE MODE
The PWM block of the ADMCF340 contains a switched reluc-
tance (SR) mode that is controlled by the
PWMSR
Pin. The
switched reluctance mode is enabled by connecting the
PWMSR
Pin to DGND. In this SR Mode, the low side PWM signals
from the three-phase timing unit assume permanently ON
states, independent of the value written to the duty-cycle
registers. The duty cycles of the high side PWM signals from the
timing unit are still determined by the three duty cycle registers.
Using the crossover feature of the output control unit, it is possible
to divert the permanently ON PWM signals to either the high
side or low side outputs. This mode is necessary because in the
typical power converter configuration for switched or variable
reluctance motors, the motor winding is connected between the
two power switches of a given inverter leg. Therefore, in order
to build up current in the motor winding, it is necessary to turn
on both switches at the same time. Typical active LO PWM
signals during operation in SR Mode are shown in Figure 8 for
operation in double update mode. It is clear that the three low
side signals (AL, BL, and CL) are permanently ON and the
three high side signals are modulated in the usual manner so
that the corresponding high side power switches are switched
between the ON and OFF states. The SR Mode can only be
enabled by connecting the
PWMSR
Pin to GND. There are no
software means by which this mode can be enabled. There is
an internal pull-up resistor on the
PWMSR
Pin so that if this
pin is left unconnected or becomes disconnected the SR Mode is
disabled. Of course, the SR Mode is disabled when the
PWMSR
Pin is tied to V
DD
.
PWM Shutdown
In the event of external fault conditions, it is essential that the
PWM system be instantaneously shut down. Two methods of
sensing a fault condition are provided by the ADMCF340. For
the first method, a low level on the
PWMTRIP
Pin initiates
an instantaneous, asynchronous (independent of DSP clock)
shutdown of the PWM controller. This places all six PWM
outputs in the OFF state, disables the PWMSYNC pulse and
associated interrupt signal, and generates a
PWMTRIP
interrupt
signal. The
PWMTRIP
Pin has an internal pull-down resistor so
that even if the pin becomes disconnected, the PWM outputs will
be disabled. The state of the
PWMTRIP
Pin can be read from
Bit 0 of the SYSSTAT Register.
The second method for detecting a fault condition is through the
I
SENSE
pins of the analog block of the ADMCF340. When the
voltage at any of the I
SENSE
pins exceeds the trip threshold
(high or low),
PWMTRIP
will be internally pulled low. The
negative edge of the internal
PWMTRIP
will generate a shut-
down in the same manner as a negative edge on pin
PWMTRIP
.
In addition, it is possible through software to initiate a PWM
shutdown by writing to the 1-bit read/write PWMSWT Register
(0x2061). Writing to this bit generates a PWM shutdown in a
manner identical to the
PWMTRIP
or I
SENSE
pins. Following
a PWM shutdown, it is possible to determine if the shutdown
was generated from hardware or software by reading the same
PWMSWT Register. Reading this register also clears it.
Restarting the PWM after a fault condition is detected requires
clearing the fault and reinitializing the PWM. Clearing the fault
requires that
PWMTRIP
returns to a HI state. After the fault has
been cleared, the PWM can be restarted by writing to registers
PWMTM, PWMCHA, PWMCHB, and PWMCHC. After the fault
is cleared and the PWM Registers are initialized, internal timing of
the three-phase timing unit will resume, and the new duty cycle
values will be latched on the next rising edge of PWMSYNC.
PWM Registers
The configuration of the PWM Registers is described at the end
of the data sheet. The parameters of the PWM block are tabu-
lated in Table IV.
ADC OVERVIEW
The ADC of the ADMCF340 is based upon the single slope
conversion technique. This approach offers an inherently mono-
tonic conversion process within the noise and stability of its
components, and there will be no missing codes.
The single slope technique has been adopted on the ADMCF340
for four channels that are simultaneously converted. Refer to
Figure 11 for the functional schematic of the ADC. The main
inputs (V1, V2, and V3) are directly connected to the ADC
converter through three front end blocks. Figure 14 shows the
block diagram of a single front end block. Each front end block has
a bipolar current amplifier (gain = –2.5) designed to acquire the
voltage on a current-sensing resistor, whose voltage can be either
positive or negative with respect to the power supply ground rail.
The fourth channel has been configured with a serially connected
8-to-1 multiplexer. Table VI shows the multiplexer input selection
codes. One of these auxiliary multiplexed channels is used to acquire
the internal voltage reference (V
REF
) for calibration purpose.
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