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參數(shù)資料
| 型號(hào)： | ADM8840 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Charge Pump Regulator & COM Driver for Color TFT Panel |
| 中文描述： | 電荷泵穩(wěn)壓器 |
| 文件頁(yè)數(shù)： | 6/10頁(yè) |
| 文件大小： | 166K |
| 代理商： | ADM8840 |
ADM8840
–6–
REV. PrG
2/03
PRELIMINARY TECHNICAL DATA
19
ADD_OUT
Voltage Adder Output Pin. This is voltage generated by adding VOUT
(unregulated output of first stage doubler) to V
CC
. This summed voltage is
then used as the supply for the gain stage which generates the Level
Translator Output Voltage. A 4.7 F capacitor is recommended for this pin.
20,21
C5+,C5-
External capacitor C5 is connected between these pins. A 3.3 F capacitor is
recommended.
23
+15VOUT
+15.0V output pin. This was derived by tripling the +5.0V regulated output. A
0.22 F capacitor is required on this pin.
29,28
C4+,C4-
External capacitor C4 is connected between these pins. A 0.22 F capacitor is
recommended.
25,24
C3+,C3-
External capacitor C3 is connected between these pins. A 0.22 F capacitor is
recommended.
27,26
C2+,C2-
External capacitor C2 is connected between these pins. A 0.22 F capacitor is
recommended.
30
-15VOUT
-15.0V output pin. This was derived by inverting the +15.0V output. A
0.22 F capacitor is required on this pin.
PIN FUNCTION DESCRIPTION (Contd.)
Pin
Mnemonic
Function
COM_OUT VOLTAGE
The COM Driver section of the ADM8840 can be used to
generate the alternate frame or line inversion of the COM
line of the LCD panel. The ADM8840 receives the COM
clock (with frequency up to 10kHz) from the controller and
allows programmable conditioning of its amplitude and
centre voltage through the use of on-board DAC’s 1 and 2.
This allows programmable elimination of display flicker
caused by the COM inversion.
The COM_OUT amplitude can be programmed from 4.0V
to 7.0V in steps of 28mV. The COM_OUT centre voltage
can be programmed from 0.9V to 2.8V in steps of 14mV.
Figure 1 below shows a typical output from the COM_OUT
pin. If programmable operation is not required the DACs can
be shutdown with the DAC1_SD and DAC2_SD pins and an
analog voltage applied to the DAC1_IN and DAC2_IN pins
to set up the amplitude and centre voltage at COM_OUT.
0.9V->1.8V->2.8V
4.0Vto7.0V
0V
Figure 1. COM_OUT Voltage
Figure 2. Power Sequence
POWER SEQUENCING
In order for the TFT panel to power up correctly, the gate
drive supplies must be sequenced such that the -15V supply
starts up before the +15V supply. The ADM8840 controls
this sequence. When the device is turned on, the ADM8840
allow the -15V output to ramp immediately, but holds off the
+15V output. It continues to do this until the negative output
has reached -3V. At this point, the positive output is enabled
and allowed to ramp to +15V. This sequence is highlighted
in figure 2.
V
CC
SHDN
+5V
+15V
-15V
-3V
t
FM15V
t
RM15V
t
F15V
t
F5V
t
R5V
t
R15V
t
DELAY2
90%
10%
90%
10%
90%
10%
t
DELAY1
CENTRE
0.VOLTAGE:
AMPLITUDE:
0V
COM_OUT
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