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參數(shù)資料
| 型號： | ADL5317ACPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/16頁 |
| 文件大?。?/td> | 541K |
| 描述： | IC CURRENT MONITOR 16LFCSP |
| 設(shè)計資源： | Interfacing ADL5317 High Side Current Mirror to a Translinear Logarithmic Amplifier in an Avalanche Photodiode Power Detector |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 功能： | 電流監(jiān)控器 |
| 檢測方法： | 高端 |
| 輸入電壓： | 10 V ~ 80 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 16-LFCSP-VQ |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁面： | 772 (CN2011-ZH PDF) |
| 其它名稱： | ADL5317ACPZ-REEL7DKR |
ADL5317
Rev. 0 | Page 14 of 16
EVALUATION BOARD
Table 4. Evaluation Board Configuration Options
Component
Function
Default Condition
VPHV, VPLV,
GND
High and Low Voltage Supply and Ground Pins.
Not Applicable
VSET
APD Bias Voltage Setting Pin. The dc voltage applied to VSET determines the APD bias
voltage at VAPD. V
APD
= 30 ?V
SET
.
Not Applicable
R11, C8
APD Input Compensation. Provides essential high frequency compensation at the VAPD
input pin.
C8 = 1 nF (size 0603)
R11 = 1 k?(size 0603)
VAPD, L1, C9
Input Interface. The evaluation board is configured to accept an input current at the SMA
connector labeled VAPD. Filtering of this current can be done using L1 and C9.
L1 = 0 ?(size 0805)
C9 = open (size 0805)
IPDM, R1
Mirror Interface. The output current at the SMA connector labeled IPDM is 1/5 the value at
VAPD. R1 allows a resistor to be installed for applications where a scaled voltage referenced
to IAPD instead of a current is desirable.
R1 = open (size 1206)
R7, R8, R9,
R10, C6, C7,
C10
Guard Options. By populating R9 and/or R10, the shell of the VAPD SMA connector is set to
the GARD potential. R7 and R8 are installed so that the guard potential can be driven by an
external source, such as the VSUM potential of the Analog Devices optical log amps. C7
filters noise from the VSET interface and provides a high frequency ac path to ground.
Additional filtering is possible by installing a capacitor at C10. C10 should equal C7.
R7 = R8 = 0 ?(size 0402)
R9 = R10 = open (size 0402)
C7 = 0.01 糉 (size 0805)
C6 = C10 = open (size 0402)
VPLV, W1,
W2, R3
Optional Supply Tracking Mode. Connecting Jumper W2 and opening Jumper W1 places
the ADL5317 into supply tracking mode. In this mode, the voltage at VAPD is typically 2 V
below V
PHV
. R3 = 100 k?for V
PLV
> 5.5 V.
R3 = 0 ?(size 0402)
W1 = open
W2 = closed
VCLH, W1,
C4, R6
Extended Linear Operating Range. Closing W1 connects Pin VPHV and Pin VCLH. This allows
for an extended linear control range of VAPD using VSET.
W1 = closed
C4 = open (size 0805)
R6 = 0 ?(size 0402)
FALT, R2
FALT Interface. R2 is a resistive pull-up that is used to create the logic signal at FALT.
R2 = 10 k?(size 0603)
C1, C2, C3,
C5, R4, R5
Supply Filtering/Decoupling.
C1 = C2 = 0.01 糉 (size 0402)
C3 = 0.1 糉 (size 0603)
C5 = 0.1 糉 (size 1206)
R4 = R5 = 0 ?(size 0402)
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