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參數(shù)資料
| 型號： | ADL5317ACPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 541K |
| 描述： | IC CURRENT MONITOR 16LFCSP |
| 設(shè)計資源： | Interfacing ADL5317 High Side Current Mirror to a Translinear Logarithmic Amplifier in an Avalanche Photodiode Power Detector |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 功能： | 電流監(jiān)控器 |
| 檢測方法： | 高端 |
| 輸入電壓： | 10 V ~ 80 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 16-LFCSP-VQ |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁面： | 772 (CN2011-ZH PDF) |
| 其它名稱： | ADL5317ACPZ-REEL7DKR |
ADL5317
Rev. 0 | Page 10 of 16
For small input currents, this pull-down must discharge not
only CGRD but also CCOMP at the VAPD pin (through the GARD
and VAPD diodes). The final 700 mV of settling for lower input
currents is dominated by the input current discharge of C
COMP
.
For larger input currents, the V
SET
amplifier pull-down discharges
only C
GRD
, since I
APD
is capable of discharging C
COMP
quickly
(see Figure 17).
Any dc load on GARD alters the gain from VSET to VAPD due
to the 20 k?source impedance. Note that the load presented by
a multimeter or oscilloscope probe is sufficient to alter the VSET to
VAPD gain, and must be taken into account.
The GARD pin is internally clamped to approximately 40 V
below VPHV to prevent device breakdown, and VAPD is
clamped to within 1 V of GARD. For this reason, any short-
circuit to ground from GARD or VAPD must be avoided for
VPHV voltages above 36 V, or device damage results.
VCLH INTERFACE
The voltage clamp high-side pin (VCLH) is typically connected
to VPHV for linear operation of the VSET interface and left
open for supply tracking mode (see the Supply Tracking Mode
section for more details). The voltage at VCLH represents a
high-side clamp above which the VSET amplifier output (and
V
APD
) is not allowed to rise. The voltage is internally set to a
temperature stable 2.0 V below V
PHV
through a 25 k?resistor.
When V
SET
is pulled up to 3 V or higher and VCLH is open,
VAPD follows 2.0 V below VPHV as VPHV is varied. This
bypasses the linear VSET interface for applications where an
adjustable high voltage supply is preferred (see the Applications
section). The 25 k?source resistance allows VCLH to be
shorted to VPHV, removing the 2.0 V high-side clamp for
extended linear operating range (up to V
PHV
1.5 V) in linear
mode. VCLH can be left open in linear mode if a fixed clamp
point is desired.
NOISE PERFORMANCE
The noise performance for the ADL5317, defined as the rms
noise current as a fraction of the output dc current, improves
with increasing signal current. This partially results from the
relationship between quiescent collector current and shot noise
in bipolar transistors. At lower signal current levels, the noise
contribution from the VSET amplifier and other noise sources
appearing at VAPD dominate the noise behavior. Filtering the
VSET interface noise through an external capacitor from GARD
to ground, as well as selecting optimal external compensation
components on VAPD, minimizes the amount of voltage noise
at VAPD that is converted to current noise at IPDM.
RESPONSE TIME
The response time for changes in signal current is fundamentally a
function of signal current, with small-signal bandwidth increasing
roughly in proportion to signal current. The value of the exter-
nal compensating capacitor on VAPD strongly affects response
time, although the value must be chosen to maintain stability
and prevent noise peaking. Response time for changes in V
SET
voltage is primarily a function of the filter capacitance at the
GARD pin. See the GARD Interface section for further details.
Figure 15 and Figure 17 show the response of the ADL5317 to
pulsed input current and VSET voltage, respectively.
DEVICE PROTECTION
Thermal and overcurrent protection are provided with fault
detection. The FALT pin is an open collector logic output
(active low) designed to assert when an overtemperature or
overcurrent condition is detected. A pull-up resistor to an
appropriate logic supply is required, and its value should be
chosen such that no more than 1 mA output current is used
when active.
When the die temperature of the ADL5317 exceeds 140癈
(typical), the current mirror shuts down, causing the bias
voltage at VAPD to be pulled down, and FALT asserts. FALT
remains asserted until the temperature falls below the trigger
temperature minus the thermal hysteresis (20癈 typical), after
which the mirror and biaser again power up. The cycle may
repeat until the cause of the fault is removed.
When the input current, I
APD
, exceeds 18 mA (typical), the
current mirror and biaser attempt to maintain the threshold
current by allowing the VAPD voltage to fall to a point of
equilibrium. In other words, the threshold current represents
the compliance of the bias voltage; in this case, the current at
which VAPD falls 500 mV below its midrange current value.
FALT asserts, but is not guaranteed to remain asserted, as
VAPD is pulled down toward ground. If V
APD
falls below ~3 V,
as in the case of a momentary short-circuit or being driven by a
programmable current source exceeding the threshold current,
bias current generators critical to device operation become satu-
rated. This causes FALT to deassert and the mirror to shut down.
The mirror does not power up until the input current falls below
the current limit of the VSET amplifier (approximately 2.5 mA),
allowing VAPD to be pulled up to its normal operating level. The
FALT pin can be grounded if the logic signal is not used.
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