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| 型號： | ADL5310ACP-R2 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LOGARITHMIC CONV DUAL 24LFCSP |
| 產(chǎn)品變化通告： | Product Discontinuance 27/July/2010 |
| 設(shè)計資源： | Interfacing ADL5315 to Translinear Logarithmic Amplifier (CN0056) Interfacing ADL5317 High Side Current Mirror to a Translinear Logarithmic Amplifier in an Avalanche Photodiode Power Detector |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 對數(shù)轉(zhuǎn)換器 |
| 應(yīng)用： | 光纖 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 24-LFCSP-VQ（4x4） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | ADL5310ACP-R2DKR |
ADL5310
Rev. A | Page 11 of 20
GENERAL STRUCTURE
The ADL5310 addresses a wide variety of interfacing conditions
to meet the needs of fiber optic supervisory systems and is
useful in many nonoptical applications. These notes explain the
structure of this unique style of translinear log amp. Figure 33
shows the key elements of one of the two identical on-board
log amps.
Q2
Q1
451
14.2k
80k
20k
6.69k
PHOTODIODE
INPUT
CURRENT
BIAS
GENERATOR
TEMPERATURE
COMPENSATION
(SUBTRACT AND
DIVIDE BY T°K)
VRDZ
COMM
VLOG
VNEG (NORMALLY GROUNDED)
VSUM
INP1
(INP2)
VREF
IREF
IREF
VBE1
VBE2
IPD
VBE1
VBE2
44
A/dec
2.5V
0.5V
04415-0-033
Figure 33. Simplified Schematic of Single Log Amp
The photodiode current IPD is received at either Pin INP1 or
Pin INP2. The voltages at these nodes are approximately equal
to the voltage on the adjacent guard pins, VSUM, as well as
reference inputs IRF1 and IRF2, due to the low offset voltage
of the JFET operational amplifiers. Transistor Q1 converts IPD
to a corresponding logarithmic voltage, as shown in Equation 1.
A finite positive value of VSUM is needed to bias the collector of
Q1 for the usual case of a single-supply voltage. This is inter-
nally set to 0.5 V, one-fifth of the 2.5 V reference voltage that
appears on Pin VREF. Both VREF pins are internally shorted,
as are both VSUM pins. The resistance at the VSUM pin is
nominally 16 kΩ; this voltage is not intended as a general bias
source.
The ADL5310 also supports the use of an optional negative
supply voltage, VN, at Pin VNEG. When VN is 0.5 V or more
negative, VSUM may be connected to ground; thus, INP1, INP2,
IRF1, and IRF2 assume this potential. This allows operation as a
voltage-input logarithmic converter by the inclusion of a series
resistor at either or both inputs. Note that the resistor setting IREF
for each channel needs to be adjusted to maintain the intercept
value. Also note that the collector-emitter voltages of Q1 and Q2
are the full VN and effects due to self-heating cause errors at
large input currents.
The input-dependent VBE1 of Q1 is compared with the reference
VBE2 of a second transistor, Q2, operating at IREF. IREF is gener-
ated externally to a recommended value of 3 A. However, other
values over a several-decade range can be used with a slight
degradation in law conformance.
THEORY
The base-emitter voltage of a bipolar junction transistor (BJT)
can be expressed by Equation 1, which immediately shows its
basic logarithmic nature:
VBE = kT/q ln(IC/IS)
(1)
where:
IC is the collector current.
IS is a scaling current, typically only 10–17 A.
kT/q is the thermal voltage, proportional to absolute
temperature (PTAT), and is 25.85 mV at 300 K.
IS is never precisely defined and exhibits an even stronger tem-
perature dependence, varying by a factor of roughly a billion
between 35°C and +85°C. Thus, to make use of the BJT as an
accurate logarithmic element, both of these temperature
dependencies must be eliminated.
The difference between the base-emitter voltages of a matched
pair of BJTs, one operating at the photodiode current IPD and the
other operating at a reference current IREF, can be written as
VBE1 – VBE2 = kT/q ln(IPD/IS) – kT/q ln(IREF/IS)
= ln(10) kT/q log10(IPD/IREF)
(2)
= 59.5 mV log10(IPD/IREF) (T = 300 K)
The uncertain, temperature-dependent saturation current, IS,
that appears in Equation 1 has therefore been eliminated. To
eliminate the temperature variation of kT/q, this difference
voltage is processed by what is essentially an analog divider.
Effectively, it puts a variable under Equation 2. The output of
this process, which also involves a conversion from voltage
mode to current mode, is an intermediate, temperature-
corrected current:
ILOG = IY log10(IPD/IREF)
(3)
where IY is an accurate, temperature-stable scaling current that
determines the slope of the function (change in current per
decade). For the ADL5310, IY is 44 A, resulting in a
temperature-independent slope of 44 A/decade for all values
of IPD and IREF. This current is subsequently converted back to a
voltage-mode output, VLOG, scaled 200 mV/decade.
It is apparent that this output should be 0 for IPD = IREF and
would need to swing negative for smaller values of input
current. To avoid this, IREF would need to be as small as the
smallest value of IPD. Accordingly, an offset voltage is added to
VLOG to shift it upward by 0.8 V when VRDZ is directly
connected to VREF. This moves the intercept to the left by four
decades (at 200 mV/decade), from 3 μA to 300 pA:
ILOG = IY log10(IPD/IINTC)
(4)
where IINTC is the operational value of the intercept current.
Because values of IPD < IINTC result in a negative VLOG, a negative
supply of sufficient value is required to accommodate this
situation.
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