參數(shù)資料
型號(hào): ADJD-J823
廠商: Avago Technologies Ltd.
英文描述: Color Management Controller with Integrated RGB Photosensor
中文描述: 色彩管理控制器集成RGB光
文件頁(yè)數(shù): 14/18頁(yè)
文件大?。?/td> 275K
代理商: ADJD-J823
14
Addressing
Each slave device on the serial bus needs to have a unique address. This is the first byte that is sent by the master-
transmitter after the START condition. The address is defined as the first seven bits of the first byte.
The eighth bit or least significant bit (LSB) determines the direction of data transfer. A ‘one’ in the LSB of the first byte
indicates that the master will read data from the addressed slave (master-receiver and slave-transmitter). A ‘zero’ in
this position indicates that the master will write data to the addressed slave (master-transmitter and slave-receiver).
A device whose address matches the address sent by the master will respond with an acknowledge for the first byte
and set itself up as a slave-transmitter or slave-receiver depending on the LSB of the first byte.
The slave address on ADJD-J823 is 0x58 (7-bits).
Figure 8. Slave Addressing
MSB
LSB
R/W
A1
A6
A5
A4
A3
A2
A0
Slave address
1
0
1
1
0
0
0
Data format
ADJD-J823 uses a register-based programming architecture. Each register has a unique address and controls a specific
function inside the chip.
To write to a register, the master first generates a START condition. Then it sends the slave address for the device it
wants to communicate with. The least significant bit (LSB) of the slave address must indicate that the master wants to
write to the slave. The addressed device will then acknowledge the master.
The master writes the register address it wants to access and waits for the slave to acknowledge. The master then
writes the new register data. Once the slave acknowledges, the master generates a STOP condition to end the data
transfer.
Figure 9. Register Byte Write Protocol
A6 A5 A4 A3 A2 A1 A0 W
A
S
A
P
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Master sends
slave address
Master writes
register address
Master writes
register data
Master will write data
Start condition
Stop condition
Slave acknowledge
A
Slave acknowledge
Slave acknowledge
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