參數(shù)資料
型號: ADJD-J823
廠商: Avago Technologies Ltd.
英文描述: Color Management Controller with Integrated RGB Photosensor
中文描述: 色彩管理控制器集成RGB光
文件頁數(shù): 12/18頁
文件大小: 275K
代理商: ADJD-J823
12
The SCL clock line synchronizes the serial data transmission on the SDA data line. It is always generated by the master.
The frequency of the SCL clock line may vary throughout the transmission as long as it still meets the minimum tim-
ing requirements.
The master by default drives the SDA data line. The slave drives the SDA data line only when sending an acknowledge
bit after the master writes data to the slave or when the master requests the slave to send data.
The SDA data line driven by the master may be implemented on the negative edge of the SCL clock line. The master
may sample data driven by the slave on the positive edge of the SCL clock line. Figure 4 shows an example of a master
implementation and how the SCL clock line and SDA data line can be synchronized.
SDA
SCL
SDA data sampled on the
positive edge of SCL
SDA data driven on the
negative edge of SCL
Figure 4. Data Bit Synchronization
Figure 5. Data Byte Transfer
SDA
SCL
MSB
LSB
1
2
8
9
ACK
1
2
8
9
NO
ACK
S
or
Sr
Sr
or
P
P
Sr
START or repeated
START condition
STOP or repeated
START condition
MSB
LSB
A complete data transfer is 8-bits long or 1-byte. Each byte is sent the most significant bit (MSB) first followed by an
acknowledge or not acknowledge bit. Each data transfer can send an unlimited number of bytes (depending on the
data format).
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