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參數(shù)資料
| 型號： | ADG792GBCPZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/24頁 |
| 文件大小： | 0K |
| 描述： | IC MUX/DEMUX TRIPLE 4X1 24LFCSP |
| 產(chǎn)品變化通告： | ADG79xx Discontinuance Notice 17/Aug/2010 |
| 標準包裝： | 1 |
| 功能： | 多路復(fù)用器/多路分解器 |
| 電路： | 3 x 4:1 |
| 導(dǎo)通狀態(tài)電阻： | 4 歐姆 |
| 電壓電源： | 單電源 |
| 電壓 - 電源，單路/雙路(±)： | 3V，5V |
| 電流 - 電源： | 1nA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 24-LFCSP-VQ（4x4） |
| 包裝： | 標準包裝 |
| 產(chǎn)品目錄頁面： | 800 (CN2011-ZH PDF) |
| 其它名稱： | ADG792GBCPZ-REELDKR |
ADG792A/ADG792G
Rev. 0 | Page 19 of 24
LDSW BIT
The LDSW bit allows the user to control the way the device
executes the commands loaded during the write operations.
The ADG792A/ADG792G execute all the commands loaded
between two successive write operations that have set the
LDSW bit high.
Setting the LDSW high for every write cycle ensures that the
device executes the command immediately after the LDSW bit
is loaded into the device. This setting is used when the desired
configuration can be achieved by sending a single command, or
when the switches and/or GPO pin are not required to be updated
at the same time. When the desired configuration requires
multiple commands with a simultaneous update, the LDSW bit
should be set low while loading the commands, except for the
last one when the LDSW bit should be set high. Once the last
command with LDSW = high is loaded, the device simultaneously
executes all commands received since the last update.
POWER ON/SOFTWARE RESET
The ADG792A/ADG792G have a software reset function
implemented by the RESETB bit from the second data byte
loaded into the device during a write operation. For normal
operation of the multiplexers and GPO pins, this bit should be
set high. When RESETB = low, or after power-up, the switches
from all multiplexers are turned off (open) and the GPO pins
are set to low.
READ OPERATION
When reading data back from the ADG792A/ADG792G, the
user must begin with an address byte and R/W bit. The switch
then acknowledges that it is prepared to transmit data by pulling
SDA low. Following this acknowledgement, the ADG792A/
ADG792G transmit two bytes on the next clock edges. These
bytes contain the status of the switches, and each byte is followed
by an acknowledge bit. A logic high bit represents a switch in
the on (close) state, and a low represents a switch in the off
(open) state. For the GPO pin (ADG792G only), the bit repre-
sents the logic value of the pin. Figure 32 illustrates the entire
read sequence.
The bit maps accompanying Figure 32 show the relationship
between the elements of the ADG792A and ADG792G (that is,
the switches and GPO pins) and the bits that represent their
status after a completed read operation.
Bit Map ADG792A
RB15
RB14
RB13
RB12
RB11
RB10
RB9
RB8
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
S1A/D1
S1B/D1
S1C/D1
S1D/D1
S2A/D2
S2B/D2
S2C/D2
S2D/D2
S3A/D3
S3B/D3
S3C/D3
S3D/D3
Bit Map ADG792G
RB15
RB14
RB13
RB12
RB11
RB10
RB9
RB8
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
S1A/D1
S1B/D1
S1C/D1
S1D/D1
S2A/D2
S2B/D2
S2C/D2
S2D/D2
S3A/D3
S3B/D3
S3C/D3
S3D/D3
GPO1
GPO2
SCL
SDA
A2
A1
A0
RB14
RB15
R/W
RB13 RB12 RB11 RB10 RB9 RB8
RB7
RB6 RB5 RB4 RB3 RB2 RB1 RB0
START
CONDITION
BY MASTER
STOP
CONDITION
BY MASTER
ADDRESS BYTE
ACKNOWLEDGE
BY SWITCH
ACKNOWLEDGE
BY SWITCH
ACKNOWLEDGE
BY SWITCH
06029-
0
15
Figure 32. Read Operation
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