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參數(shù)資料
| 型號： | ADG3246BCP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 2.5 V/3.3 V, 10-Bit, 2-Port Level Translating, Bus Switch |
| 中文描述： | 10-BIT DRIVER, TRUE OUTPUT, QCC24 |
| 封裝： | 4 X 4 MM, MO-220-VGGD-2, CSP-24 |
| 文件頁數(shù)： | 4/12頁 |
| 文件大?。?/td> | 353K |
| 代理商： | ADG3246BCP |
PRELIMINARY TECHNICAL DATA
REV. Pr
C
–4–
ADG3246
TERMINOLOGY
V
CC
GND
V
INH
V
INL
I
I
I
OZ
I
OL
V
P
Positive Power Supply Voltage
Ground (0 V) Reference
Minimum Input Voltage for Logic 1
Maximum Input Voltage for Logic 0
Input Leakage Current at the Control Inputs
OFF State Leakage Current. It is the maximum leakage current at the switch pin in the OFF state.
ON State Leakage Current. It is the maximum leakage current at the switch pin in the ON state.
Max Pass Voltage. The max pass voltage relates to the clipped output voltage of an NMOS device when the switch
input voltage is equal to the supply voltage.
Ohmic Resistance Offered by a Switch in the ON State. It is measured at a given voltage by forcing a specified
amount of current through the switch.
On Resistance Match between Any Two Channels, i.e., R
ON
Max - R
ON
Min
OFF Switch Capacitance
ON Switch Capacitance
Control Input Capacitance. This consists of
BE
and
SEL
.
Quiescent Power Supply Current. It is measured when all control inputs are at a logic HIGH or LOW level and
the switches are OFF.
Extra Power Supply Current Component for the
BE
Control Input when the Input is not Driven at the Supplies
Data Propagation Delay through the Switch in the ON State. Propagation delay is related to the RC time constant
R
ON
×
C
L
, where C
L
is the load capacitance.
Bus Enable Times. These are times taken to cross the V
T
voltage at the switch output when the switch turns on in
response to the control signal,
BE
.
Bus Disable Times. This is the time taken to place the switch in the high impedance OFF state in response to the con-
trol signal. It is measured as the time taken for the output voltage to change by V from the original quiescent level,
with reference to the logic level transition at the control input. (Refer to Figure 3 for enable and disable times.)
Maximum Rate at which Data Can Be Passed through the Switch
Peak-to-Peak Value of the Sum of the Deterministic and Random Jitter of the Switch Channel
Operating Frequency of Bus Enable. This is the maximum frequency at which Bus Enable (
BE
) can be toggled.
R
ON
R
ON
C
X
OFF
C
X
ON
C
IN
I
CC
I
CC
t
PLH
, t
PHL
t
PZH
, t
PZL
t
PHZ
, t
PLZ
Max Data Rate
Channel Jitter
f
BEx
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