VIH Logic input high voltage at Pin A1 to Pin A8. " />
參數(shù)資料
型號: ADG3123BRUZ
廠商: Analog Devices Inc
文件頁數(shù): 12/12頁
文件大?。?/td> 0K
描述: IC XLATOR 8CH LOG-HV 20-TSSOP
標準包裝: 75
邏輯功能: 變換器
位數(shù): 8
輸入類型: CMOS
輸出類型: 電壓
通道數(shù): 8
輸出/通道數(shù)目: 1
差分 - 輸入:輸出: 無/無
傳輸延遲(最大): 125ns
電源電壓: 2.3 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應商設備封裝: 20-TSSOP
包裝: 管件
產品目錄頁面: 802 (CN2011-ZH PDF)
Data Sheet
ADG3123
Rev. B | Page 9 of 12
TERMINOLOGY
VIH
Logic input high voltage at Pin A1 to Pin A8.
VIL
Logic input low voltage at Pin A1 to Pin A8.
IIL
Leakage current at Pin A1 to Pin A8.
CI
Capacitance measured at Pin A1 to Pin A8.
VOH
Logic output high voltage at Pin Y1 to Pin Y8.
VOL
Logic output low voltage at Pin Y1 to Pin Y8.
Ro
Output impedance.
tPLH
Propagation delay through the part measured between the input
signal applied to any one channel and its corresponding output
for a low-to-high transition (see Figure 2).
tPHL
Propagation delay through the part measured between the input
signal applied to any one channel and its corresponding output
for a high-to-low transition (see Figure 2).
tR
Rise time of the output signal at Pin Y1 to Pin Y8 (see Figure 2).
tF
Fall time of the output signal at the Pin Y1 to Pin Y8
(see Figure 2).
FO
Frequency of the signal applied to the A1 to A8 input pins.
VDDA
Input voltage used to generate the high logic levels for Y1 to Y6
outputs.
VDDB
Positive power supply voltage. Also used to generate the high
logic levels for Y7 to Y8 outputs.
VSS
Negative power supply voltage. It is used to generate the low
logic level for Y1 to Y8 outputs.
GND
Ground (0 V) reference.
IDDA
Supply current at the VDDA pin.
IDDB
Supply current at the VDDB pin.
ISS
Supply current at the VSS pin.
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