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參數(shù)資料
| 型號： | ADF4360-9BCPZRL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SYNTHESIZER W/ADJ VCO 24LFCSP |
| 標準包裝： | 1 |
| 類型： | 扇出配送，整數(shù)-N，合成器（RF） |
| PLL： | 是 |
| 輸入： | CMOS |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 400MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 24-LFCSP-VQ（4x4） |
| 包裝： | 標準包裝 |
| 產(chǎn)品目錄頁面： | 551 (CN2011-ZH PDF) |
| 其它名稱： | ADF4360-9BCPZRL7DKR |
ADF4360-9
Data Sheet
Rev. C | Page 12 of 24
OUTPUT STAGE
The RFOUTA and RFOUTB pins of the ADF4360 family are
connected to the collectors of an NPN differential pair driven
by buffered outputs of the VCO, as shown in Figure 19. To
allow the user to optimize the power dissipation vs. the output
power requirements, the tail current of the differential pair is
programmable via Bit PL1 and Bit PL2 in the control latch.
Four current levels can be set: 3.5 mA, 5 mA, 7.5 mA, and 11 mA.
These levels give output power levels of 9 dBm, 6 dBm,
3 dBm, and 0 dBm, respectively, using the correct shunt inductor
to VDD and ac coupling into a 50 load. Alternatively, both
outputs can be combined in a 1 + 1:1 transformer or a 180°
microstrip coupler (see the Output Matching section).
Another feature of the ADF4360 family is that the supply
current to the RF output stage is shut down until the part
achieves lock, as measured by the digital lock detect circuitry.
This is enabled by the mute-till-lock detect (MTLD) bit in the
control latch.
VCO
RFOUTA
RFOUTB
BUFFER
07139-
020
Figure 19. RF Output Stage
DIVOUT STAGE
The output multiplexer on the ADF4360 family allows the user
to access various internal points on the chip. The state of DIVOUT
is controlled by D3, D2, and D1 in the control latch. The full
truth table is shown in Figure 23. Figure 20 shows the DIVOUT
section in block diagram form.
R COUNTER OUTPUT
N COUNTER OUTPUT
A COUNTER OUTPUT
DGND
CONTROL
MUX
DIVOUT
DVDD
A COUNTER/2 OUTPUT
07139-
018
Figure 20. DIVOUT Circuit
The primary use of this pin is to derive the lower frequencies
from the VCO by programming various divider values to the
auxiliary A divider. Values ranging from 2 to 31 are possible.
The duty cycle of this output is 1/A times 100%, with the logic
high pulse width equal to the inverse of the VCO frequency.
That is,
Pulse Width [seconds] = 1/fVCO (Frequency [Hz])
See Figure 21 for a graphical description. By selecting the
divide-by-2 function, this divided down frequency can in turn
be divided by 2 again. This provides a 50% duty cycle in contrast to
the A counter output, which may be more suitable for some
applications (see Figure 21).
fVCO
fVCO/A (A = 4)
fVCO/2A (A = 4)
07139-
021
Figure 21. DIVOUT Waveforms
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