參數(shù)資料
型號(hào)： ADF4360-9BCPZRL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 19/24頁(yè)
文件大?。?/td> 0K
描述： IC SYNTHESIZER W/ADJ VCO 24LFCSP
標(biāo)準(zhǔn)包裝： 1
類(lèi)型： 扇出配送，整數(shù)-N，合成器（RF）
PLL： 是
輸入： CMOS
輸出： 時(shí)鐘
電路數(shù)： 1
比率 - 輸入:輸出： 1:2
差分 - 輸入:輸出： 無(wú)/無(wú)
頻率 - 最大： 400MHz
除法器/乘法器： 是/無(wú)
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 24-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 24-LFCSP-VQ（4x4）
包裝： 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁(yè)面： 551 (CN2011-ZH PDF)
其它名稱(chēng)： ADF4360-9BCPZRL7DKR
ADF4360-9
Data Sheet
Rev. C | Page 4 of 24
Parameter
B Version
Unit
Conditions/Comments
Frequency Pushing (Open Loop)
0.24
MHz/V typ
Frequency Pulling (Open Loop)
10
Hz typ
Into 2.00 VSWR load
Harmonic Content (Second)
16
dBc typ
Harmonic Content (Third)
21
dBc typ
Output Power5, 7
9/0
dBm typ
Using tuned load, programmable in 3 dB steps;
Output Power5, 8
14/9
dBm typ
Using 50 resistors to VVCO, programmable in
3 dB steps; see Figure 33
Output Power Variation
±3
dB typ
VCO Tuning Range
1.25/2.5
V min/V max
VCO NOISE CHARACTERISTICS
VCO Phase Noise Performance9,10
91
dBc/Hz typ
@ 10 kHz offset from carrier
117
dBc/Hz typ
@ 100 kHz offset from carrier
139
dBc/Hz typ
@ 1 MHz offset from carrier
140
dBc/Hz typ
@ 3 MHz offset from carrier
147
dBc/Hz typ
@ 10 MHz offset from carrier
Normalized In-Band Phase Noise 10, 11
218
dBc/Hz typ
In-Band Phase Noise10, 11
110
dBc/Hz typ
@ 1 kHz offset from carrier
RMS Integrated Jitter12
1.4
ps typ
Measured at RFOUTA
Spurious Signals Due to PFD Frequency13
75
dBc typ
DIVOUT CHARACTERISTICS12
Integrated Jitter Performance
(Integrated from 100 Hz to 1 GHz)
VCO frequency = 320 MHz to 380 MHz
DIVOUT = 180 MHz
1.4
ps rms
A = 2, A output selected
DIVOUT = 95 MHz
1.4
ps rms
A = 2, A/2 output selected
DIVOUT = 80 MHz
1.4
ps rms
A = 2, A/2 output selected
DIVOUT = 52 MHz
1.4
ps rms
A = 3, A/2 output selected (VCO = 312 MHz,
PFD = 1.6 MHz)
DIVOUT = 45 MHz
1.4
ps rms
A = 4, A/2 output selected
DIVOUT = 10 MHz
1.6
ps rms
A = 18, A/2 output selected (VCO = 360 MHz,
PFD = 1.6 MHz)
DIVOUT Duty Cycle
A Output
1/A × 100
% typ
Divide-by-A selected
A/2 Output
50
% typ
Divide-by-A/2 selected
1
Operating temperature range is 40°C to +85°C.
2
Guaranteed by design. Sample tested to ensure compliance.
3
ICP is internally modified to maintain constant loop gain over the frequency range.
4
TA = 25°C; AVDD = DVDD = VVCO = 3.3 V.
5
Unless otherwise stated, these characteristics are guaranteed for VCO core power = 5 mA. L1, L2 = 270 nH, 470 resistors to GND in parallel with L1, L2.
6
Jumping from 90 MHz to 108 MHz. PFD frequency = 200 kHz; loop bandwidth = 10 kHz.
7
For more detail on using tuned loads, see the Output Matching section.
8
Using 50 resistors to VVCO into a 50 load.
9
The noise of the VCO is measured in open-loop conditions. L1, L2 = 56 nH.
10
The phase noise is measured with the EV-ADF4360-9EB1Z evaluation board and the Agilent E5052A signal source analyzer.
11
fREFIN = 10 MHz; fPFD = 1 MHz; N = 360; loop B/W = 40 kHz. The normalized phase noise floor is estimated by measuring the in-band phase noise at the output of the
VCO and subtracting 20logN (where N is the N divider value) and 10logfPFD. PNSYNTH = PNTOT 10logfPFD 20logN.
12
The jitter is measured with the EV-ADF4360-9EB1Z evaluation board and the Agilent E5052A signal source analyzer. A low noise TCXO provides the REFIN for the
synthesizer, and the jitter is measured over the instrument’s jitter measurement bandwidth. fREFIN = 10 MHz; fPFD = 1 MHz; N = 360; loop BW = 40 kHz, unless otherwise
noted.
13
The spurious signals are measured with the EV-ADF4360-9EB1Z evaluation board and the Agilent E5052A signal source analyzer. The spectrum analyzer provides the
REFIN for the synthesizer; fREFIN = 10 MHz @ 0 dBm. fREFIN = 10 MHz; fPFD = 1 MHz; N = 360; loop BW = 40 kHz.
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