- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1989 > ADF4350BCPZ-RL (Analog Devices Inc)IC SYNTH PLL VCO FN/IN 32LFCSP PDF資料下載
參數(shù)資料
| 型號(hào)： | ADF4350BCPZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 16/32頁(yè) |
| 文件大小： | 0K |
| 描述： | IC SYNTH PLL VCO FN/IN 32LFCSP |
| 產(chǎn)品變化通告： | ADF4350, ADF4905/6 N-counter Change 05/Mar/2012 |
| 設(shè)計(jì)資源： | Broadband Low EVM Direct Conversion Transmitter (CN0134) Broadband Low EVM Direct Conversion Transmitter Using LO Divide-by-2 Modulator (CN0144) Using low noise linear drop-out regulators to power wideband PLL & VCO IC's (CN0147) |
| 標(biāo)準(zhǔn)包裝： | 5,000 |
| 類型： | 扇出配送，分?jǐn)?shù)-N，整數(shù)-N，時(shí)鐘/頻率合成器（RF） |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:3 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 4.4GHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 帶卷 (TR) |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)當(dāng)前第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)
ADF4350
Rev. A | Page 23 of 32
FAST LOCK—LOOP FILTER TOPOLOGY
To use fast-lock mode, the damping resistor in the loop filter
is reduced to of its value while in wide bandwidth mode. To
achieve the wider loop filter bandwidth, the charge pump
current increases by a factor of 16 and to maintain loop sta-
bility the damping resistor must be reduced a factor of .
To enable fast lock, the SW pin is shorted to the GND pin by
settings Bits [DB16:DB15] in Register 3 to 0, 1. The following
two topologies are available:
The damping resistor (R1) is divided into two values (R1
and R1A) that have a ratio of 1:3 (see Figure 31).
An extra resistor (R1A) is connected directly from SW, as
shown in Figure 32. The extra resistor is calculated such
that the parallel combination of an extra resistor and the
damping resistor (R1) is reduced to of the original value
of R1 (see Figure 32).
ADF4350
CP
SW
C1
C2
R2
R1
R1A
C3
VCO
0
732
5-
0
18
Figure 31. Fast-Lock Loop Filter Topology—Topology 1
ADF4350
CP
SW
C1
C2
R2
R1
R1A
C3
VCO
0
732
5-
0
19
Figure 32. Fast-Lock Loop Filter Topology—Topology 2
SPUR MECHANISMS
This section describes the three different spur mechanisms that
arise with a fractional-N synthesizer and how to minimize them
in the ADF4350.
Fractional Spurs
The fractional interpolator in the ADF4350 is a third-order
Σ-Δ modulator (SDM) with a modulus (MOD) that is program-
mable to any integer value from 2 to 4095. In low spur mode
(dither enabled) the minimum allowable value of MOD is 50.
The SDM is clocked at the PFD reference rate (fPFD) that allows
PLL output frequencies to be synthesized at a channel step
resolution of fPFD/MOD.
In low noise mode (dither disabled) the quantization noise from
the Σ-Δ modulator appears as fractional spurs. The interval
between spurs is fPFD/L, where L is the repeat length of the code
sequence in the digital Σ-Δ modulator. For the third-order
modulator used in the ADF4350, the repeat length depends on
the value of MOD, as listed in Table 6.
Table 6. Fractional Spurs with Dither Disabled
Condition (Dither Disabled)
Repeat
Length
Spur Interval
If MOD is divisible by 2, but not 3
2 × MOD
Channel step/2
If MOD is divisible by 3, but not 2
3 × MOD
Channel step/3
If MOD is divisible by 6
6 × MOD
Channel step/6
Otherwise
MOD
Channel step
In low spur mode (dither enabled), the repeat length is extend-
ed to 221 cycles, regardless of the value of MOD, which makes
the quantization error spectrum look like broadband noise.
This may degrade the in-band phase noise at the PLL output
by as much as 10 dB. For lowest noise, dither disabled is a better
choice, particularly when the final loop bandwidth is low
enough to attenuate even the lowest frequency fractional spur.
Integer Boundary Spurs
Another mechanism for fractional spur creation is the inter-
actions between the RF VCO frequency and the reference
frequency. When these frequencies are not integer related (the
point of a fractional-N synthesizer) spur sidebands appear on
the VCO output spectrum at an offset frequency that corres-
ponds to the beat note or difference frequency between an
integer multiple of the reference and the VCO frequency. These
spurs are attenuated by the loop filter and are more noticeable
on channels close to integer multiples of the reference where the
difference frequency can be inside the loop bandwidth, there-
fore, the name integer boundary spurs.
Reference Spurs
Reference spurs are generally not a problem in fractional-N
synthesizers because the reference offset is far outside the loop
bandwidth. However, any reference feed-through mechanism
that bypasses the loop may cause a problem. Feed through of
low levels of on-chip reference switching noise, through the
RFIN pin back to the VCO, can result in reference spur levels as
high as –90 dBc. PCB layout needs to ensure adequate isolation
between VCO traces and the input reference to avoid a possible
feed through path on the board.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADF4351BCPZ | IC SYNTH PLL VCO 32LFCSP |
| ADF4360-0BCPZRL7 | IC SYNTHESIZER VCO 24LFCSP |
| ADF4360-1BCPZRL7 | IC SYNTHESIZER VCO 24LFCSP |
| ADF4360-2BCPZRL7 | IC SYNTHESIZER VCO 24LFCSP |
| ADF4360-3BCPZRL7 | IC SYNTHESIZER VCO 24LFCSP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADF4350BCPZ-RL7 | 功能描述:IC SYNTH PLL VCO FN/IN 32LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
| ADF4350BCPZ-U6 | 制造商:Analog Devices 功能描述: |
| ADF4350EB1Z | 制造商:Analog Devices 功能描述:AD EVAL BOARD - Bulk |
| ADF4351 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Wideband Synthesizer |
| ADF4351BCPZ | 功能描述:IC SYNTH PLL VCO 32LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。