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參數(shù)資料
| 型號： | ADF4216BRUZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL FREQ SYNTHESIZER 20TSSOP |
| 產(chǎn)品變化通告： | ADF4213,16 Discontinuation 15/May/2012 |
| 標準包裝： | 1 |
| 類型： | 時鐘/頻率合成器（RF/IF） |
| PLL： | 是 |
| 輸入： | CMOS |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:1 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 1.2GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 20-TSSOP |
| 包裝： | 標準包裝 |
| 其它名稱： | ADF4216BRUZ-RLDKR |
REV. 0
ADF4216/ADF4217/ADF4218
–5–
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic
Function
1VDD1
Positive Power Supply for the RF Section. Decoupling capacitors to the analog ground plane should be
placed as close as possible to this pin. VDD1 should have a value of between 2.7 V and 5.5 V. VDD1 must
have the same potential as VDD2.
2VP1
Power Supply for the RF Charge Pump. This should be greater than or equal to VDD.
3CPRF
Output from the RF Charge Pump. When enabled this provides
±ICP to the external loop lter, which in
turn drives the external VCO.
4
DGNDRF
Ground Pin for the RF Digital Circuitry.
5RFINA
Input to the RF Prescaler. This low-level input signal is normally ac-coupled to the external VCO.
6RFINB
Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with a small
bypass capacitor, typically 100 pF.
7
AGNDRF
Ground Pin for the RF Analog Circuitry.
8
REFIN
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent input resis-
tance of 100 k
. This input can be driven from a TTL or CMOS crystal oscillator or it can be ac-coupled.
9
DGNDIF
Ground Pin for the IF Digital (Interface and Control Circuitry).
10
MUXOUT
This multiplexer output allows either the IF/RF lock detect, the scaled RF, or the scaled Reference Fre-
quency to be accessed externally. See Table V.
11
CLK
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched
into the 22-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
12
DATA
Serial Data Input. The serial data is loaded MSB rst with the two LSBs being the control bits. This input is
a high impedance CMOS input.
13
LE
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of
the four latches, the latch being selected using the control bits.
14
AGNDIF
Ground Pin for the IF Analog Circuitry.
15
IFINB
Complementary Input to the IF Prescaler. This point should be decoupled to the ground plane with a small
bypass capacitor, typically 100 pF.
16
IFINA
Input to the IF Prescaler. This low-level input signal is normally ac-coupled to the external VCO.
17
DGNDIF
Ground Pin for the IF Digital, Interface, and Control Circuitry.
18
CPIF
Output from the IF Charge Pump. When enabled this provides
±ICP to the external loop lter, which in turn
drives the external VCO.
19
VP2
Power Supply for the IF Charge Pump. This should be greater than or equal to VDD.
20
VDD2
Positive Power Supply for the IF, Interface, and Oscillator Sections. Decoupling capacitors to the analog
ground plane should be placed as close as possible to this pin. VDD2 should have a value of between 2.7 V
and 5.5 V. VDD2 must have the same potential as VDD1.
PIN CONFIGURATION
REF
IN
CLK
DATA
LE
MUXOUT
RF
INA
CP
RF
AGND
RF
INB
V
DD1
DGND
RF
V
DD2
V
P1
DGND
IF
AGND
IF
INB
IF
INA
DGND
IF
CP
IF
V
P2
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
TSSOP
ADF4216/
ADF4217/
ADF4218
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| ADF4217L | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ADF4217L/18L/19L: Dual Low Power Frequency Synthesizers Data Sheet (Rev. B. 7/02) |
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