參數(shù)資料
型號: ADF4193WCCPZ-RL7
廠商: Analog Devices Inc
文件頁數(shù): 10/32頁
文件大小: 0K
描述: IC PLL FREQ SYNTHESIZER 32LFCSP
標準包裝: 1,500
類型: 時鐘/頻率合成器,RF
PLL:
輸入: CMOS,TTL
輸出: 時鐘
電路數(shù): 1
比率 - 輸入:輸出: 2:1
差分 - 輸入:輸出: 是/無
頻率 - 最大: 3.5GHz
除法器/乘法器: 是/是
電源電壓: 2.7 V ~ 3.3 V
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 32-LFCSP-VQ
包裝: 帶卷 (TR)
ADF4193
Data Sheet
Rev. F | Page 18 of 32
FUNCTION REGISTER (R3)
05328-
026
DB15
0
DB14
0
DB13
0
DB12
0
DB11
0
DB10
0
DB9
0
DB8
0
DB7
0
DB6
1
DB5
F3
DB4
1
DB3
F1
DB2
C3 (0)
DB1
C2 (1)
DB0
C1 (1)
PF
D
P
OLA
R
ITY
R
ESER
VED
CP
O
G
ND
RESERVED
CONTROL
BITS
0
1
F1
NEGATIVE
POSITIVE
PFD POLARITY
0
1
F3
CPO/CPO GND
NORMAL
CPO GND
Figure 32. Function Register (R3)
R3, the function register (C3, C2, C1 set to 0, 1, 1, respectively),
only needs to be programmed during the initialization sequence
CPO GND
When the CPO GND bit is low, the charge pump outputs
are internally pulled to ground. This is invoked during the
initialization sequence to discharge the loop filter capacitors.
For normal operation, this bit should be high.
PFD Polarity
This bit should be set to 1 for positive polarity and set to 0 for
negative polarity.
Reserved Bits
The Bit DB15 to Bit DB6 are reserved bits and should be
programmed to hex code 001, and Reserved Bit DB4 should be
set to 1.
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