參數(shù)資料
型號(hào): ADF4193BCPZ-RL7
廠商: ANALOG DEVICES INC
元件分類: XO, clock
英文描述: Low Phase Noise, Fast Settling PLL Frequency Synthesizer
中文描述: PLL FREQUENCY SYNTHESIZER, 3500 MHz, QCC32
封裝: 5 X 5 MM, ROHS COMPLIANT, MO-220VHHD-2, LFCSP-32
文件頁(yè)數(shù): 7/28頁(yè)
文件大小: 437K
代理商: ADF4193BCPZ-RL7
ADF4193
Pin No.
23
Rev. B | Page 7 of 28
Mnemonic
R
SET
Description
Connecting a resistor between this pin and GND sets the charge pump output current. The nominal voltage bias at
the R
SET
pin is 0.55 V. The relationship between I
CP
and R
SET
is
I
CP
= 0.25/
R
SET
So, with
R
SET
= 2.4 kΩ,
I
CP
= 104 μA.
Power Supply Pin for the Charge Pump. Nominally 5 V, should be at the same voltage at V
P
1. A 0.1 μF decoupling
capacitor to ground should be placed as close as possible to this pin.
Differential Amplifier’s Negative Input Pin.
Differential Charge Pump’s Negative Output Pin. Should be connected to AIN and the loop filter.
Fast Lock Switch 2. This switch is closed to SW
GND
while the SW1/2 timeout counter is active.
Common for SW1 and SW2 Switches. Should be connected to the ground plane.
Fast Lock Switch 1. This switch is closed to SW
GND
while the SW1/2 timeout counter is active.
Differential Charge Pump’s Positive Output Pin. Should be connected to AIN+ and the loop filter.
Differential Amplifier’s Positive Input Pin.
Power Supply Pin for the Differential Amplifier. This can range from 5.0 V to 5.5 V. A 0.1 μF decoupling capacitor to
ground should be placed as close as possible to this pin. Also requires a 10 μF decoupling capacitor to ground.
24
V
P
2
25
26
27
28
29
30
31
32
AIN
CP
OUT
SW2
SW
GND
SW1
CP
OUT+
AIN+
V
P
3
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