- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9160 > ADF4150BCPZ (Analog Devices Inc)IC PLL SYNTHESIZER 24-LFCSP PDF資料下載
參數(shù)資料
| 型號： | ADF4150BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL SYNTHESIZER 24-LFCSP |
| 標準包裝： | 1 |
| 類型： | 分數(shù) N，整數(shù) N，頻率合成器（RF） |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 4.4GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-WFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 24-LFCSP-WQ（4x4） |
| 包裝： | 托盤 |
第1頁第2頁第3頁當前第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
ADF4150
Data Sheet
Rev. A | Page 12 of 28
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4150 allows the user
to access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 (for details, see
Figure 22). Figure 17 shows the MUXOUT section in block
diagram form.
Figure 17. MUXOUT Schematic
INPUT SHIFT REGISTERS
The ADF4150 digital section includes a 10-bit RF R counter,
a 16-bit RF N counter, a 12-bit FRAC counter, and a 12-bit
modulus counter. Data is clocked into the 32-bit shift register
on each rising edge of CLK. The data is clocked in MSB first.
Data is transferred from the shift register to one of six latches
on the rising edge of LE. The destination latch is determined
by the state of the three control bits (C3, C2, and C1) in the
shift register. These are the 3 LSBs, DB2, DB1, and DB0, as
shown in Figure 2. The truth table for these bits is shown in
Table 5. Figure 19 shows a summary of how the latches are
programmed.
Table 5. C3, C2, and C1 Truth Table
Control Bits
C3
C2
C1
Register
0
Register 0 (R0)
0
1
Register 1 (R1)
0
1
0
Register 2 (R2)
0
1
Register 3 (R3)
1
0
Register 4 (R4)
1
0
1
Register 5 (R5)
PROGRAM MODES
Figure 20 through Figure 25 show how the program modes are
to be set up in the ADF4150.
A number of settings in the ADF4150 are double buffered.
These include the modulus value, phase value, R counter
value, reference doubler, reference divide-by-2, and current
setting. This means that two events have to occur before the
part uses a new value of any of the double-buffered settings.
First, the new value is latched into the device by writing to the
appropriate register. Second, a new write must be performed
on Register R0. For example, any time the modulus value is
updated, Register R0 must be written to, thus ensuring the
modulus value is loaded correctly. Divider select in Register 4
(R4) is also double buffered, but only if DB13 of Register 2 (R2)
is high.
OUTPUT STAGE
to the collectors of an NPN differential pair driven by buffered
outputs of the VCO, as shown in Figure 18. To allow the user
to optimize the power dissipation vs. the output power require-
ments, the tail current of the differential pair is programmable
by Bit D2 and Bit D1 in Register 4 (R4). Four current levels may
be set. These levels give output power levels of 4 dBm, 1 dBm,
+2 dBm, and +5 dBm, respectively, using a 50 resistor to
AVDD and ac coupling into a 50 load. Alternatively, both
outputs can be combined in a 1 + 1:1 transformer or a 180°
microstrip coupler (see the Output Matching section). If the
outputs are used individually, the optimum output stage
consists of a shunt inductor to AVDD.
Another feature of the ADF4150 is that the supply current
to the RF output stage can be shut down until the part
achieves lock as measured by the digital lock detect circuitry.
This is enabled by the mute-till-lock detect (MTLD) bit in
Register 4 (R4).
Figure 18. Output Stage
DGND
DVDD
CONTROL
MUX
MUXOUT
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
R COUNTER OUTPUT
N COUNTER OUTPUT
DGND
RESERVED
THREE-STATE-OUTPUT
DVDD
R COUNTER INPUT
08226-
013
VCO
RFOUT+
RFOUT–
BUFFER/
DIVIDE-BY-1/
-2/-4/-8/-16
08226-
014
相關PDF資料 |
PDF描述 |
|---|---|
| MS27472P24B35P | CONN RCPT 128POS WALL MNT W/PINS |
| ADF4212LBCPZ | IC PLL FREQ SYNTHESIZER 20LFCSP |
| M83723/84W2212N | CONN RCPT 12POS JAM NUT W/SCKT |
| VI-BWP-MY-F3 | CONVERTER MOD DC/DC 13.8V 50W |
| 7WBD383CMX1TCG | IC BUS SWITCH 1X1 8LLGA |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADF4150BCPZ-RL7 | 功能描述:IC PLL FREQ SYNTH 5.0GHZ 24LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應商設備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4150HV | 制造商:AD 制造商全稱:Analog Devices 功能描述:High Voltage, Fractional-N |
| ADF4150HVBCPZ | 功能描述:IC FRACTION-N FREQ SYNTH 32LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應商設備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4150HVBCPZ-RL7 | 功能描述:IC FRACTION-N FREQ SYNTH 32LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應商設備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4151 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Fractional-N/Integer-N PLL Synthesizer |
發(fā)布緊急采購，3分鐘左右您將得到回復。