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參數(shù)資料
| 型號(hào)： | ADF4150BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 3/28頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL SYNTHESIZER 24-LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 分?jǐn)?shù) N，整數(shù) N，頻率合成器（RF） |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 4.4GHz |
| 除法器/乘法器： | 是/無(wú) |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-WFQFN 裸露焊盤(pán)，CSP |
| 供應(yīng)商設(shè)備封裝： | 24-LFCSP-WQ（4x4） |
| 包裝： | 托盤(pán) |
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Data Sheet
ADF4150
Rev. A | Page 11 of 28
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 14. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REFIN pin
on power-down.
Figure 14. Reference Input Stage
RF N DIVIDER
The RF N divider allows a division ratio in the PLL feedback
path. Division ratio is determined by INT, FRAC, and MOD
values, which build up this divider.
INT, FRAC, MOD, AND R COUNTER RELATIONSHIP
The INT, FRAC, and MOD values, in conjunction with the R
counter, make it possible to generate output frequencies that
are spaced by fractions of the PFD frequency. See the RF
Synthesizer—A Worked Example section for more informa-
tion. The RF VCO frequency (RFOUT) equation is
RFOUT = fPFD × (INT + (FRAC/MOD))
(1)
where:
RFOUT is the output frequency of external voltage controlled
oscillator (VCO).
INT is the preset divide ratio of the binary 16–bit counter
(23 to 65535 for 4/5 prescaler, 75 to 65535 for 8/9 prescaler).
MOD is the preset fractional modulus (2 to 4095).
FRAC is the numerator of the fractional division (0 to MOD 1).
fPFD = REFIN × [(1 + D)/(R × (1 + T))]
(2)
where:
REFIN is the reference input frequency.
D is the REFIN doubler bit.
T is the REFIN divide-by-2 bit (0 or 1).
R is the preset divide ratio of the binary 10-bit programmable
reference counter (1 to 1023).
Figure 15. RF INT Divider
INT N MODE
If the FRAC = 0 and DB8 in Register 2 (LDF) is set to 1, the
synthesizer operates in integer-N mode. The DB8 in Register 2
(LDF) should be set to 1 to get integer-N digital lock detect.
Additionally, lower phase noise is possible if the anti-backlash
pulse width is reduced to 3 ns. This mode is not valid for
fractional-N applications.
R COUNTER
The 10–bit R counter allows the input reference frequency
(REFIN) to be divided down to produce the reference clock
to the PFD. Division ratios from 1 to 1023 are allowed.
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The phase frequency detector (PFD) takes inputs from the R
counter and N counter and produces an output proportional to
the phase and frequency difference between them. Figure 16 is
a simplified schematic of the phase frequency detector. The
PFD includes a programmable delay element that sets the width
of the antibacklash pulse, which can be either 6 ns (default, for
fractional-N applications) or 3 ns (for integer-N mode). This
pulse ensures there is no dead zone in the PFD transfer function,
and gives a consistent reference spur level.
Figure 16. PFD Simplified Schematic
BUFFER
TO R COUNTER
REFIN
100k
NC
SW2
SW3
NO
NC
SW1
POWER-DOWN
CONTROL
08226-
010
THIRD ORDER
FRACTIONAL
INTERPOLATOR
FRAC
VALUE
MOD
REG
INT
REG
RF N DIVIDER
N = INT + FRAC/MOD
FROM
VCO OUTPUT/
OUTPUT DIVIDERS
TO PFD
N COUNTER
08226-
011
U3
CLR2
Q2
D2
U2
DOWN
UP
HIGH
CP
–IN
+IN
CHARGE
PUMP
DELAY
CLR1
Q1
D1
U1
08226-
012
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